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Searched refs:ADD (Results 1 – 25 of 79) sorted by relevance

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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dx86_64.s25 ADD AL,0x11 label
26 ADD AH,0x11 label
27 ADD SPL,0x11 label
28 ADD R8B,0x11 label
29 ADD R12B,0x11 label
46 ADD EAX,[R8] label
47 ADD R8D,[R8] label
48 ADD RAX,[R8] label
49 ADD EAX,[0x22222222+RIP] label
50 ADD EAX,[RBP+0x00] label
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/
Dx86-64.s25 ADD AL,0x11 label
26 ADD AH,0x11 label
27 ADD SPL,0x11 label
28 ADD R8B,0x11 label
29 ADD R12B,0x11 label
46 ADD EAX,[R8] label
47 ADD R8D,[R8] label
48 ADD RAX,[R8] label
49 ADD EAX,[0x22222222+RIP] label
50 ADD EAX,[RBP+0x00] label
[all …]
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-metag/
Dshared.d11 .*: 82120860 ADD A0.2,A0.2,#0x410c
17 .*: 82120780 ADD A0.2,A0.2,#0x40f0
25 .*: 86080026 ADD A0FrP,A0StP,#0
28 .*: 82000040 ADD A0StP,A0StP,#0x8
30 .*: 830b0660 ADD A1LbP,A1LbP,#0x60cc
33 .*: 00000200 ADD D0Re0,D0Re0,D0Ar6
36 .*: 0306ffc0 ADD D1Re0,D1Re0,#0xdff8
Dshared.s7 ADD A0FrP,A0StP,#0
10 ADD A0StP,A0StP,#8
12 ADD A1LbP,A1LbP,#LO(__GLOBAL_OFFSET_TABLE__+4)
15 ADD D0Re0,D0Re0,D0Ar6
18 ADD D1Re0,D1Re0,#LO(_local_var1@GOTOFF)
Dstub_shared.d11 .*: 82120700 ADD A0.2,A0.2,#0x40e0
17 .*: 82120620 ADD A0.2,A0.2,#0x40c4
25 .*: 86080026 ADD A0FrP,A0StP,#0
28 .*: 82000040 ADD A0StP,A0StP,#0x8
30 .*: 830b0500 ADD A1LbP,A1LbP,#0x60a0
Dstub_pic_shared.d10 .*: 82120660 ADD A0.2,A0.2,#0x40cc
16 .*: 82120580 ADD A0.2,A0.2,#0x40b0
23 .*: 82180100 ADD A0.3,A0.3,#0x20
30 .*: 821ffee0 ADD A0.3,A0.3,#0xffdc
Dstub_shared.s6 ADD A0FrP,A0StP,#0
9 ADD A0StP,A0StP,#8
11 ADD A1LbP,A1LbP,#LO(__GLOBAL_OFFSET_TABLE__+4)
Dstub_pic_app.d10 .*: 02049720 ADD D0Re0,D0Re0,#0x92e4
16 .*: 821496e0 ADD A0.2,A0.2,#0x92dc
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/
Dguard.s15 ADD r1,r2,r3
16 ADD/AL r1,r2,r3
17 ADD/tx r1,r2,r3
19 ADD/XT r1,r2,r3
20 ADD/XF r1,r2,r3
22 ADD/tf r1,r2,r3
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/
Dtls.s2 ADD D1Ar1,D1Ar1,#(_a@TLSGD)
3 ADD D1Ar1,D1Ar1,#(_b@TLSLDM)
5 ADD D0Re0,D0Re0,#LO(_b@TLSLDO)
8 ADD D0Re0,D0Re0,#LO(_b@TLSIENONPIC)
10 ADD D0Re0,D0Re0,#LO(_b@TLSLE)
Dtls.d9 0: 03180000 ADD D1Ar1,D1Ar1,#0
11 4: 03180000 ADD D1Ar1,D1Ar1,#0
15 c: 02000000 ADD D0Re0,D0Re0,#0
21 18: 02000000 ADD D0Re0,D0Re0,#0
25 20: 02000000 ADD D0Re0,D0Re0,#0
Dlabelarithmetic.s1 lbl1: ADD TXL1START, CPC0, #(loop_start-lbl1)
3 ADD A0.0, A0.0, #(loop_end-lbl2)
Dlabelarithmetic.d10 .*: 862c0420 ADD TXL1START,CPC0,#0x10
14 .*: 820000a0 ADD A0StP,A0StP,#0x14
Dmetafpu21ext.s73 FD ADD FX.0,FX.2,FX.4
74 F ADD FX.3,FX.1,FX.0
75 FL ADD FX.6,FX.4,FX.2
76 FDI ADD FX.0,FX.2,FX.4
77 FI ADD FX.3,FX.1,FX.0
78 FLI ADD FX.6,FX.4,FX.2
Dmetafpu21ext.d81 .*: f1008821 FD ADD FX\.0,FX\.2,FX\.4
82 .*: f1184001 F ADD FX\.3,FX\.1,FX\.0
83 .*: f1310441 FL ADD FX\.6,FX\.4,FX\.2
84 .*: f10088a1 FDI ADD FX\.0,FX\.2,FX\.4
85 .*: f1184081 FI ADD FX\.3,FX\.1,FX\.0
86 .*: f13104c1 FLI ADD FX\.6,FX\.4,FX\.2
Dmetafpu21.s2 F ADD FX.0,D0Re0,D0Re0
6 F ADD FX.0,D0.7,D1.7
9 F ADD FX.1,D0Re0,RD
12 F ADD FX.1,D0.7,A0FrP
15 F ADD FX.2,D0.7,D0Re0
18 F ADD FX.3,D0Re0,A1LbP
21 F ADD FX.3,D0.7,D0.7
24 F ADD FX.4,D0Re0,D1Re0
27 F ADD FX.4,D0.7,D1.7
30 F ADD FX.5,D0Re0,RD
[all …]
Dmetafpu21.d10 .*: 04000120 F ADD FX\.0,D0Re0,D0Re0
14 .*: 0401df21 F ADD FX\.0,D0\.7,D1\.7
17 .*: 04082121 F ADD FX\.1,D0Re0,RD
20 .*: 0409f321 F ADD FX\.1,D0\.7,A0FrP
23 .*: 0411c120 F ADD FX\.2,D0\.7,D0Re0
26 .*: 04180321 F ADD FX\.3,D0Re0,A1LbP
29 .*: 0419cf20 F ADD FX\.3,D0\.7,D0\.7
32 .*: 04201121 F ADD FX\.4,D0Re0,D1Re0
35 .*: 0421df21 F ADD FX\.4,D0\.7,D1\.7
38 .*: 04282121 F ADD FX\.5,D0Re0,RD
[all …]
Dmetacore12.s4 ADD D0Re0,D0.7,D1.7
5 ADD D0.7,D0Re0,A1.7 define
6 ADD D0.7,D0.7,D0Re0 define
7 ADD D0.7,D0.7,A0.7 define
8 ADD D1Re0,D1Re0,D0.7
9 ADD D1Re0,D1.7,A1.7
10 ADD D1.7,D1Re0,A1LbP define
11 ADD D1.7,D1Re0,A0FrP define
12 ADD D1.7,D1.7,RD define
202 ADD TXENABLE,D0Re0,#0xff
[all …]
Dmetacore21.s4 ADD D0Re0,D0.7,D1.7
5 ADD D0.7,D0Re0,A1.7 define
6 ADD D0.7,D0.7,D0Re0 define
7 ADD D0.7,D0.7,A0.7 define
8 ADD D1Re0,D1Re0,D0.7
9 ADD D1Re0,D1.7,A1.7
10 ADD D1.7,D1Re0,A1LbP define
11 ADD D1.7,D1Re0,A0FrP define
12 ADD D1.7,D1.7,RD define
140 ADD PC,D0Re0,#0x7f
[all …]
/toolchain/binutils/binutils-2.25/include/opcode/
Dm88k.h256 #define ADD 4 macro
258 #define SUBU ADD+1
259 #define SUBB ADD+2
260 #define SUBUB ADD+3
261 #define SUB ADD+4
263 #define AND_ ADD+5
264 #define OR ADD+6
265 #define XOR ADD+7
266 #define CMP ADD+8
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/
Din_mlib.asm2 ADD #AA,a
3 ADD #BB,b
4 ADD #CC,a
Dmacro.s34 ADD ABC,A
39 ADDX #100 ; ADD #100,A
/toolchain/binutils/binutils-2.25/gold/
Daarch64-reloc.def47 … Y, -1, 0,0 , 0,11 , Symbol::ABSOLUTE_REF , ADD )
67 … Y, -1, 0,0 , 0,11 , Symbol::TLS_REF , ADD )
71 … Y, -1, 0,0 , 0,11 , Symbol::TLS_REF , ADD )
74 … Y, -1, 0,24 , 12,23 , Symbol::TLS_REF , ADD )
75 … Y, -1, 0,0 , 0,11 , Symbol::TLS_REF , ADD )
90 … Y, -1, 0,24 , 12,23 , Symbol::TLS_REF , ADD )
91 … Y, -1, 0,12 , 0,11 , Symbol::TLS_REF , ADD )
92 … Y, -1, 0,0 , 0,11 , Symbol::TLS_REF , ADD )
97 … Y, -1, 0,0 , 0,11 , Symbol::TLS_REF , ADD )
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Darmv8-a-it-bad.l10 …b instructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX …
15 …ining 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
16 …ining 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
17 …ining 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
18 …ining 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/
Dlist-insns.s51 ADD $12,$223,$1
52 ADD $122,$203,255

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