| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
| D | metafpu21.s | 2 F ADD FX.0,D0Re0,D0Re0
3 F ADDLT FX.0,D0Re0,D0.7
4 F ADDVS FX.0,D0Re0,RD
5 F ADDHI FX.0,D0.7,A1LbP
6 F ADD FX.0,D0.7,D1.7
7 F ADDLE FX.0,D0.7,A0FrP
8 F ADDEQ FX.1,D0Re0,D0.7
9 F ADD FX.1,D0Re0,RD
10 F ADDLE FX.1,D0.7,D0Re0
11 F ADDMI FX.1,D0.7,D1Re0
[all …]
|
| D | metafpu21.d | 10 .*: 04000120 F ADD FX\.0,D0Re0,D0Re0
11 .*: 04000f38 F ADDLT FX\.0,D0Re0,D0\.7
12 .*: 0400212f F ADDVS FX\.0,D0Re0,RD
13 .*: 0401c333 F ADDHI FX\.0,D0\.7,A1LbP
14 .*: 0401df21 F ADD FX\.0,D0\.7,D1\.7
15 .*: 0401f33d F ADDLE FX\.0,D0\.7,A0FrP
16 .*: 04080f22 F ADDEQ FX\.1,D0Re0,D0\.7
17 .*: 04082121 F ADD FX\.1,D0Re0,RD
18 .*: 0409c13c F ADDLE FX\.1,D0\.7,D0Re0
19 .*: 0409d12b F ADDMI FX\.1,D0\.7,D1Re0
[all …]
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | epiphany-opc.c | 48 #define F(f) & epiphany_cgen_ifld_table[EPIPHANY_##f] macro
54 16, 16, 0xff, { { F (F_SIMM8) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
58 32, 32, 0xff, { { F (F_SIMM24) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
62 …16, 16, 0xe3ff, { { F (F_DC_15_3) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC…
66 …{ { F (F_DC_31_3) }, { F (F_RN_X) }, { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_DC_15_3) }, { F…
70 …fe3ff, { { F (F_DC_31_3) }, { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_DC_15_3) }, { F (F_RN6) …
74 …16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F…
78 …F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_ADDSUBX) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_R…
82 …, { { F (F_DC_22_2) }, { F (F_ADDSUBX) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F…
86 …16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { F (F_WORDSIZE) }, { F (F_STORE) }, …
[all …]
|
| D | mt-opc.c | 78 #define F(f) & mt_cgen_ifld_table[MT_##f] macro
84 …32, 32, 0xff000fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, …
88 …32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, {…
92 …32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, {…
96 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU24) }, { 0 } }
100 …32, 32, 0xfff00000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_DR) }, …
104 …32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, …
108 …32, 32, 0xffff0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }…
112 …32, 32, 0xff0f0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) },…
116 …32, 32, 0xff0f0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) },…
[all …]
|
| D | iq2000-opc.c | 43 #define F(f) & iq2000_cgen_ifld_table[IQ2000_##f] macro
49 …32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_SHAMT) }, { F (F_FUN…
53 …32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) },…
57 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } }
61 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } }
65 …32, 32, 0xfc000020, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) },…
69 …32, 32, 0xffe0003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) },…
73 …32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUN…
77 …32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUN…
81 …32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) },…
[all …]
|
| D | m32r-opc.c | 66 #define F(f) & m32r_cgen_ifld_table[M32R_##f] macro
72 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
76 …32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, …
80 …32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, …
84 …32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, …
88 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
92 …32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, …
96 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
100 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
104 …32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, …
[all …]
|
| D | or1k-opc.c | 45 #define F(f) & or1k_cgen_ifld_table[OR1K_##f] macro
51 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_DISP26) }, { 0 } }
55 …32, 32, 0xffff07ff, { { F (F_OPCODE) }, { F (F_RESV_25_10) }, { F (F_R3) }, { F (F_RESV_10_11) }, …
59 …32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_OP_25_5) }, { F (F_RESV_20_5) }, { F (F_UIMM16) }, …
63 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_OP_25_5) }, { F (F_RESV_20_21) }, { 0 } }
67 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RESV_25_26) }, { 0 } }
71 …32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_OP_25_2) }, { F (F_RESV_23_8) }, { F (F_UIMM16) }, …
75 …32, 32, 0xfc1f0000, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_20_4) }, { F (F_OP_16_1) }, { F …
79 …32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_20_4) }, { F (F_OP_16_1) }, { F …
83 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
[all …]
|
| D | frv-opc.c | 892 #define F(f) & frv_cgen_ifld_table[FRV_##f] macro
898 …32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NUL…
902 …32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_ICCI_1…
906 …32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NUL…
910 …32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1)…
914 …32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, {…
918 …32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) …
922 …2, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F…
926 … 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, {…
930 …2, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F…
[all …]
|
| D | xstormy16-opc.c | 43 #define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f] macro
49 …32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_LMEM8) }, { F (F_IMM16…
53 …32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_HMEM8) }, { F (F_IMM16…
57 16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } }
61 16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } }
65 …16, 16, 0xfe08, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F…
69 …, 32, 0xfe08f000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, {…
73 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { 0 } }
77 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } }
81 16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } }
[all …]
|
| D | pdp11-dis.c | 31 #define F info->stream macro
55 FPRINTF (F, "-%o", -n); in print_signed_octal()
57 FPRINTF (F, "%o", n); in print_signed_octal()
69 FPRINTF (F, "r%d", reg); break; in print_reg()
70 case 6: FPRINTF (F, "sp"); break; in print_reg()
71 case 7: FPRINTF (F, "pc"); break; in print_reg()
79 FPRINTF (F, "fr%d", freg); in print_freg()
95 FPRINTF (F, "("); in print_operand()
97 FPRINTF (F, ")"); in print_operand()
106 FPRINTF (F, "$"); in print_operand()
[all …]
|
| D | mep-opc.c | 190 #define F(f) & mep_cgen_ifld_table[MEP_##f] macro
196 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
200 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
204 …32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }…
208 …, 32, 0xf00ff0ff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_C5N4) }, {…
212 …32, 32, 0xf00ff000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }…
216 …32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }…
220 …32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }…
224 …32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }…
228 …32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }…
[all …]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| D | x86-64-avx512f_vl.s | 1 # Check 64bit AVX512{F,VL} instructions
6 vaddpd %xmm28, %xmm29, %xmm30 # AVX512{F,VL}
7 vaddpd %xmm28, %xmm29, %xmm30{%k7} # AVX512{F,VL}
8 vaddpd %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
9 vaddpd (%rcx), %xmm29, %xmm30 # AVX512{F,VL}
10 vaddpd 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{F,VL}
11 vaddpd (%rcx){1to2}, %xmm29, %xmm30 # AVX512{F,VL}
12 vaddpd 2032(%rdx), %xmm29, %xmm30 # AVX512{F,VL} Disp8
13 vaddpd 2048(%rdx), %xmm29, %xmm30 # AVX512{F,VL}
14 vaddpd -2048(%rdx), %xmm29, %xmm30 # AVX512{F,VL} Disp8
[all …]
|
| D | x86-64-avx512f_vl-opts.s | 1 # Check 64bit AVX512{F,VL} swap instructions
6 vmovapd %xmm29, %xmm30 # AVX512{F,VL}
7 vmovapd.s %xmm29, %xmm30 # AVX512{F,VL}
8 vmovapd %xmm29, %xmm30{%k7} # AVX512{F,VL}
9 vmovapd.s %xmm29, %xmm30{%k7} # AVX512{F,VL}
10 vmovapd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
11 vmovapd.s %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
12 vmovapd %xmm29, %xmm30 # AVX512{F,VL}
13 vmovapd.s %xmm29, %xmm30 # AVX512{F,VL}
14 vmovapd %xmm29, %xmm30{%k7} # AVX512{F,VL}
[all …]
|
| D | x86-64-avx512f_vl-wig.s | 1 # Check 64bit AVX512{F,VL} WIG instructions
6 vpmovsxbd %xmm29, %xmm30 # AVX512{F,VL}
7 vpmovsxbd %xmm29, %xmm30{%k7} # AVX512{F,VL}
8 vpmovsxbd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
9 vpmovsxbd (%rcx), %xmm30 # AVX512{F,VL}
10 vpmovsxbd 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
11 vpmovsxbd 508(%rdx), %xmm30 # AVX512{F,VL} Disp8
12 vpmovsxbd 512(%rdx), %xmm30 # AVX512{F,VL}
13 vpmovsxbd -512(%rdx), %xmm30 # AVX512{F,VL} Disp8
14 vpmovsxbd -516(%rdx), %xmm30 # AVX512{F,VL}
[all …]
|
| D | avx512f_vl.s | 1 # Check 32bit AVX512{F,VL} instructions
6 vaddpd %xmm4, %xmm5, %xmm6{%k7} # AVX512{F,VL}
7 vaddpd %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
8 vaddpd (%ecx), %xmm5, %xmm6{%k7} # AVX512{F,VL}
9 vaddpd -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{F,VL}
10 vaddpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
11 vaddpd 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
12 vaddpd 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{F,VL}
13 vaddpd -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
14 vaddpd -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{F,VL}
[all …]
|
| D | avx512f_vl-opts.s | 1 # Check 32bit AVX512{F,VL} swap instructions
6 vmovapd %xmm5, %xmm6{%k7} # AVX512{F,VL}
7 vmovapd.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
8 vmovapd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
9 vmovapd.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
10 vmovapd %xmm5, %xmm6{%k7} # AVX512{F,VL}
11 vmovapd.s %xmm5, %xmm6{%k7} # AVX512{F,VL}
12 vmovapd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
13 vmovapd.s %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
14 vmovapd %ymm5, %ymm6{%k7} # AVX512{F,VL}
[all …]
|
| D | avx512f_vl-wig.s | 1 # Check 32bit AVX512{F,VL} WIG instructions
6 vpmovsxbd %xmm5, %xmm6{%k7} # AVX512{F,VL}
7 vpmovsxbd %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
8 vpmovsxbd (%ecx), %xmm6{%k7} # AVX512{F,VL}
9 vpmovsxbd -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
10 vpmovsxbd 508(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
11 vpmovsxbd 512(%edx), %xmm6{%k7} # AVX512{F,VL}
12 vpmovsxbd -512(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
13 vpmovsxbd -516(%edx), %xmm6{%k7} # AVX512{F,VL}
14 vpmovsxbd %xmm5, %ymm6{%k7} # AVX512{F,VL}
[all …]
|
| D | immed64.d | 9 [ ]*[0-9a-fA-F]+:[ ]+ff 50 04[ ]+callq? +\*0x4\(%rax\)
10 [ ]*[0-9a-fA-F]+:[ ]+ff 90 08 00 00 00[ ]+callq? +\*0x8\(%rax\)
11 [ ]*[0-9a-fA-F]+:[ ]+ff 90 00 00 00 00[ ]+callq? +\*0x0\(%rax\)
12 [ ]*[0-9a-fA-F]+:[ ]+67 ff 50 04[ ]+(addr32 )?callq? +\*0x4\(%eax\)
13 [ ]*[0-9a-fA-F]+:[ ]+67 ff 90 08 00 00 00[ ]+(addr32 )?callq? +\*0x8\(%eax\)
14 [ ]*[0-9a-fA-F]+:[ ]+67 ff 90 00 00 00 00[ ]+(addr32 )?callq? +\*0x0\(%eax\)
15 [ ]*[0-9a-fA-F]+:[ ]+b0 04[ ]+movb? +\$0x4,%al
16 [ ]*[0-9a-fA-F]+:[ ]+b0 08[ ]+movb? +\$0x8,%al
17 [ ]*[0-9a-fA-F]+:[ ]+b0 00[ ]+movb? +\$0x0,%al
18 [ ]*[0-9a-fA-F]+:[ ]+66 b8 04 00[ ]+movw? +\$0x4,%ax
[all …]
|
| D | immed32.d | 9 [ ]*[0-9a-fA-F]+:[ ]+ff 50 04[ ]+calll? +\*0x4\(%eax\)
10 [ ]*[0-9a-fA-F]+:[ ]+ff 90 08 00 00 00[ ]+calll? +\*0x8\(%eax\)
11 [ ]*[0-9a-fA-F]+:[ ]+ff 90 00 00 00 00[ ]+calll? +\*0x0\(%eax\)
12 [ ]*[0-9a-fA-F]+:[ ]+67 ff 57 04[ ]+(addr16 )?calll? +\*0x4\(%bx\)
13 [ ]*[0-9a-fA-F]+:[ ]+67 ff 97 08 00[ ]+(addr16 )?calll? +\*0x8\(%bx\)
14 [ ]*[0-9a-fA-F]+:[ ]+67 ff 97 00 00[ ]+(addr16 )?calll? +\*0x0\(%bx\)
15 [ ]*[0-9a-fA-F]+:[ ]+b0 04[ ]+movb? +\$0x4,%al
16 [ ]*[0-9a-fA-F]+:[ ]+b0 08[ ]+movb? +\$0x8,%al
17 [ ]*[0-9a-fA-F]+:[ ]+b0 00[ ]+movb? +\$0x0,%al
18 [ ]*[0-9a-fA-F]+:[ ]+66 b8 04 00[ ]+movw? +\$0x4,%ax
[all …]
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-pe/ |
| D | longsecn-3.d | 10 0 \.(text|bss ) [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
12 …1 \.text\.very\.long\.section\.name [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[…
14 2 \.data [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
16 3 \.data\$1 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
18 4 \.rodata\$1 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
20 5 \.data\$123 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
22 6 \.rodata\$123 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
24 7 \.data\$123456789 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
26 8 \.rodata\$123456789 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
28 9 \.data\.very\.long\.section [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
[all …]
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| D | longsecn-5.d | 10 0 \.(text|bss ) [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
12 …1 \.text\.very\.long\.section\.name [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[…
14 2 \.data [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
16 3 \.data\$1 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
18 4 \.rodata\$1 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
20 5 \.data\$123 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
22 6 \.rodata\$123 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
24 7 \.data\$123456789 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
26 8 \.rodata\$123456789 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
28 9 \.data\.very\.long\.section [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
[all …]
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| D | longsecn-4.d | 10 0 \.(text|bss ) [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
12 1 \.text\.ve [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
14 2 \.data [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
16 3 \.data\$1 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
18 4 \.rodata\$ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
20 5 \.data\$12 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
22 6 \.rodata\$ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
24 7 \.data\$12 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
26 8 \.rodata\$ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
28 9 \.data\.ve [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9]
[all …]
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| /toolchain/binutils/binutils-2.25/gas/config/ |
| D | rx-parse.y | 71 #define F(val,pos,sz) rx_field (val, pos, sz) macro
93 #define IMM_(v,pos,size) F (immediate (v, RXREL_SIGNED, pos, size), pos, 2); \
98 #define NIMM(v,pos) F (immediate (v, RXREL_NEGATIVE, pos, 32), pos, 2)
99 #define NBIMM(v,pos) F (immediate (v, RXREL_NEGATIVE_BORROW, pos, 32), pos, 2)
102 F (displacement (v, msz), pos, 2)
239 { B1 (0x20); F ($1, 4, 4); PC1 ($3); }
268 B1 (0x20); F ($1, 4, 4); PC1 ($2);
276 { B2 (0x3c, 0); rx_field5s2 ($6); F ($8, 9, 3); O1 ($4); }
278 { B2 (0xf8, 0x04); F ($8, 8, 4); DSP ($6, 6, BSIZE); O1 ($4);
283 { B2 (0x3d, 0); rx_field5s2 ($6); F ($8, 9, 3); O1 ($4); }
[all …]
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| D | mips16-intermix.d | 6 .* l F .text 0+[0-9a-f]+ m32_static_l
7 .* l F .text 0+[0-9a-f]+ 0xf0 m16_static_l
8 .* l F .text 0+[0-9a-f]+ m32_static1_l
9 .* l F .text 0+[0-9a-f]+ 0xf0 m16_static1_l
10 .* l F .text 0+[0-9a-f]+ m32_static32_l
11 .* l F .text 0+[0-9a-f]+ 0xf0 m16_static32_l
12 .* l F .text 0+[0-9a-f]+ m32_static16_l
13 .* l F .text 0+[0-9a-f]+ 0xf0 m16_static16_l
14 .* l F .text 0+[0-9a-f]+ __fn_stub_m16_d
15 .* l F .text 0+[0-9a-f]+ m32_static_d
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/ |
| D | immed64.d | 9 [ ]*[0-9a-fA-F]+:[ ]+ff 50 04[ ]+callq? +\*0x4\(%rax\)
10 [ ]*[0-9a-fA-F]+:[ ]+ff 90 08 00 00 00[ ]+callq? +\*0x8\(%rax\)
11 [ ]*[0-9a-fA-F]+:[ ]+ff 90 00 00 00 00[ ]+callq? +\*0x0\(%rax\)
12 [ ]*[0-9a-fA-F]+:[ ]+67 ff 50 04[ ]+(addr32 )?callq? +\*0x4\(%eax\)
13 [ ]*[0-9a-fA-F]+:[ ]+67 ff 90 08 00 00 00[ ]+(addr32 )?callq? +\*0x8\(%eax\)
14 [ ]*[0-9a-fA-F]+:[ ]+67 ff 90 00 00 00 00[ ]+(addr32 )?callq? +\*0x0\(%eax\)
15 [ ]*[0-9a-fA-F]+:[ ]+b0 04[ ]+movb? +\$0x4,%al
16 [ ]*[0-9a-fA-F]+:[ ]+b0 08[ ]+movb? +\$0x8,%al
17 [ ]*[0-9a-fA-F]+:[ ]+b0 00[ ]+movb? +\$0x0,%al
18 [ ]*[0-9a-fA-F]+:[ ]+66 b8 04 00[ ]+movw? +\$0x4,%ax
[all …]
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