Home
last modified time | relevance | path

Searched refs:FFF (Results 1 – 2 of 2) sorted by relevance

/toolchain/binutils/binutils-2.25/opcodes/
Dv850-opc.c1060 #define FFF (SR2 + 1) macro
1064 #define CCCC (FFF + 1)
1818 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0,…
1821 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V85…
1824 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PRO…
1826 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V8…
1892 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3_UP },
/toolchain/binutils/binutils-2.25/cpu/
Dip2k.opc326 *valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */