/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
D | loop_temps.s | 209 I2 = P2; define 233 I2 = P2; define 235 R4 = [I0++] || R5 = [I2--]; 238 A1 -= R4.H*R5.H, A0 += R4.L*R5.L (IS) || R4 = [I0++] || R5 = [I2--]; 263 I2 = P2; define 266 R5 = [I2--]; 271 A1 -= R4.H*R5.H, A0 += R4.L*R5.L (IS) || R4 = [I0++] || R5 = [I2--]; 273 R0 = (A0 += A1) || I2 += M0; 278 A1 = A0 = 0 || [I2--] = R5 280 I2 += 4; [all …]
|
D | parallel.d | 12 10: 0a ce 0a 08 R4 = EXTRACT \(R2, R1.L\) \(Z\) \|\| I2 -= M0 \|\| NOP; 38 78: 30 cc 3f 40 A1 = ABS A1 \|\| FP = \[SP\] \|\| R3 = \[I2--\]; 44 90: 02 cc 10 a8 R4.L = R2.H \+ R0.L \(S\) \|\| B\[FP\] = R0 \|\| R2.H = W\[I2--\]; 50 a8: 05 cc 01 98 R4.L = R0 \+ R1 \(RND20\) \|\| B\[P2\] = R0 \|\| R5.L = W\[I2--\]; 56 c0: 05 cc 01 04 R2.L = R0 \+ R1 \(RND12\) \|\| R1 = B\[SP\] \(X\) \|\| \[I2--\] = R7; 62 d8: 25 cc 0a 44 R2.H = R1 - R2 \(RND12\) \|\| R1 = B\[P2\] \(Z\) \|\| W\[I2\+\+\] = R4.H; 138 208: 02 c9 03 58 A1 -= R0.L \* R3.H \(IS\) \|\| R2.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R0; 140 210: 02 c8 17 58 A1 -= R2.L \* R7.H \|\| R3.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R1; 142 218: 03 c8 f5 25 R7.L = \(A0 = R6.H \* R5.L\) \|\| R4.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R2; 144 …220: c3 c8 0a 24 R0.L = \(A0 = R1.H \* R2.L\) \(TFU\) \|\| R5.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R… [all …]
|
D | parallel.s | 4 r4 = extract (r2, r1.L) (z) || I2 -= M0; 22 a1 = aBs A1 || fp = [sp] || r3 = [I2--]; 34 r2.L = R0 + R1 (rnd12) || r1 = b [sp] (x) || [I2--]= r7; 37 r2.h = R1 - R2 (Rnd12) || r1 = b [p2] (z) || w [I2++] = R4.H; 89 a1 -= r2.l * r7.h || r3.l = w [i0] || [I2++M2] =R1; 92 r0.L = (A0 = r1.h * R2.l) (tfu) || r5.l = w [i0] || [I2++m2] = R3; 93 R2.L = (a0 += r5.L * r4.L) || r6.l = w [i0] || [I2++m2] = R4; 105 R0 = (A0 = R1.L * R2.L) || R1.L = W [I2--] || [i3++m3] = r1; 106 R2 = (A0 = r1.l * r2.l) (is) || R1.L = W [I2--] || [i3++m3] = r0; 107 r4 = (a0 += r7.h * r6.L) || R2.L = W [I2--] || r0.h = w[i0]; [all …]
|
D | load.s | 13 I2.h = 0xf204; 71 R3 = [I2--]; 101 R2.h = w [I2 --]; 109 R6.L = W [I2++];
|
D | store.d | 26 28: 12 9e \[I2\+\+\] = R2; 33 32: d7 9e W\[I2--\] = R7.H; 40 3c: b1 9e W\[I2--\] = R1.L;
|
D | load.d | 14 18: 52 e1 04 f2 I2.H = 0xf204;.* 61 9a: 93 9c R3 = \[I2--\]; 85 c6: d2 9c R2.H = W\[I2--\]; 91 ce: 36 9c R6.L = W\[I2\+\+\];
|
D | parallel4.d | 20 30: 17 cc 02 22 R1 = BYTEOP3P \(R1:0, R3:2\) \(LO, R\) \|\| \[I2\] = R0 \|\| NOP; 22 38: 37 cc 02 24 R2 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\) \|\| \[I2\+\+\] = R0 \|\| NOP; 24 40: 0c cc 7f 45 R5 = A1.L \+ A1.H, R2 = A0.L \+ A0.H \|\| \[I2--\] = R0 \|\| NOP;
|
D | store.s | 26 [I2++] = R2; 44 W[I2--] = R1.l;
|
D | move2.s | 76 R2 = I2; 94 P2 = I2; 113 A1.X = I2; 134 I2 = SP; define 138 I2 = A1.X; define 173 I2 = B1; define
|
D | parallel2.d | 46 98: 27 c8 40 18 R1.H = A1 \(S2RND\) \|\| R0 = \[I2 \+\+ M0\] \|\| NOP; 48 a0: 07 c8 40 18 R1.H = A1 \|\| R0 = \[I2 \+\+ M1\] \|\| NOP; 50 a8: 67 c9 80 38 R2.H = A1, R2.L = A0 \(IH\) \|\| R0 = \[I2 \+\+ M2\] \|\| NOP; 52 b0: 07 c8 80 38 R2.H = A1, R2.L = A0 \|\| R0 = \[I2 \+\+ M3\] \|\| NOP;
|
D | move2.d | 62 6c: 92 30 R2 = I2; 78 8c: 92 32 P2 = I2; 94 ac: 92 38 A1.X = I2; 110 cc: 56 34 I2 = SP; 114 d4: 12 35 I2 = A1.X; 142 10c: d1 34 I2 = B1;
|
D | arithmetic.d | 42 56: 6a 9f I2 \+= 0x4;.* 78 9c: 6a 9e I2 \+= M2; 179 1cc: 66 9f I2 -= 0x2;.*
|
D | pseudo.s | 25 DBG I2;
|
D | arithmetic.s | 47 I2 += 4; 224 I2 -= 2;
|
D | parallel3.d | 132 1f0: 0e c8 37 c9 R5 = \(A1 -= R6.H \* R7.H\), A0 \+= R6.L \* R7.L \|\| \[I2\] = R0 \|\| NOP; 134 …1f8: 0c c8 b7 e0 R3 = \(A1 = R6.H \* R7.H\), R2 = \(A0 = R6.L \* R7.L\) \|\| \[I2\+\+\] = R0 \|\|… 136 …200: 9c c8 1f e9 R5 = \(A1 = R3.H \* R7.H\) \(M\), R4 = \(A0 \+= R3.L \* R7.L\) \(FU\) \|\| \[I2-…
|
D | move.d | 11 6: b2 34 M2 = I2;
|
D | pseudo.d | 25 24: 12 f8 DBG I2;
|
D | vector2.s | 655 A1=R2.L*R1.L, A0=R2.H*R1.H || R2.H=W[I2++] || [I3++]=R3 ; 658 A1+=R0.L*R2.H,A0+=R0.L*R2.L || R2.L=W[I2++] || R0=[I1--] ; 662 R1=PACK(R1.H,R0.H) || [I0++]=R0 || R2.L=W[I2++] ;
|
D | vector2.d | 462 …718: 00 c8 11 06 A1 = R2.L \* R1.L, A0 = R2.H \* R1.H \|\| R2.H = W\[I2\+\+\] \|\| \[I3\+\+\] = R… 464 …720: 01 c8 02 48 A1 \+= R0.L \* R2.H, A0 \+= R0.L \* R2.L \|\| R2.L = W\[I2\+\+\] \|\| R0 = \[I1-… 468 730: 04 ce 01 c2 R1 = PACK \(R1.H, R0.H\) \|\| \[I0\+\+\] = R0 \|\| R2.L = W\[I2\+\+\]; 470 738: 8b c8 9a 2f R6 = \(A0 \+= R3.H \* R2.H\) \(FU\) \|\| I2 -= M0 \|\| NOP;
|
/toolchain/binutils/binutils-2.25/opcodes/ |
D | mips-opc.c | 327 #define I2 INSN_ISA2 macro 752 {"bc1fl", "p", 0x45020000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 }, 757 {"bc1tl", "p", 0x45030000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 }, 762 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, 765 {"beql", "s,t,p", 0x50000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 }, 766 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, 769 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3, 0, I37 }, 770 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, 773 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3, 0, I37 }, 774 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, [all …]
|
D | ia64-opc-i.c | 26 #define I2 IA64_TYPE_I, 2 macro 173 I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY 175 I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL 195 I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY 197 I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL 217 I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY 219 I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL 290 #undef I2
|
D | arm-dis.c | 4325 unsigned int I2 = (given & 0x00000800u) >> 11; in print_insn_thumb32() local 4330 offset |= !(I2 ^ S) << 22; in print_insn_thumb32()
|
/toolchain/binutils/binutils-2.25/gas/doc/ |
D | c-s390.texi | 337 @item RI format: <insn> R1,I2 340 | OpCode | R1 |OpCd| I2 | 345 @item RIE format: <insn> R1,R3,I2 348 | OpCode | R1 | R3 | I2 |////////| OpCode | 353 @item RIL format: <insn> R1,I2 356 | OpCode | R1 |OpCd| I2 | 369 @item RIS format: <insn> R1,I2,M3,D4(B4) 372 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 425 @item RSI format: <insn> R1,R3,I2 428 | OpCode | R1 | R3 | I2 | [all …]
|
D | c-bfin.texi | 215 The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
|
/toolchain/binutils/binutils-2.25/cpu/ |
D | frv.opc | 285 /* I2 */ UNIT_NIL, /* no I2 or I3 unit */ 320 /* I2 */ UNIT_NIL, /* no I2 or I3 unit */ 352 /* I2 */ UNIT_NIL, /* no I2 or I3 unit */ 384 /* I2 */ UNIT_I2,
|