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Searched refs:M0 (Results 1 – 22 of 22) sorted by relevance

/toolchain/binutils/binutils-2.25/opcodes/
Dia64-opc-m.c24 #define M0 IA64_TYPE_M, 0 macro
104 {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY},
105 {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY},
106 {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}, EMPTY},
107 {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}, EMPTY},
109 {"invala", M0, OpX3X4X2 (0, 0, 0, 1), {}, EMPTY},
110 {"fwb", M0, OpX3X4X2 (0, 0, 0, 2), {}, EMPTY},
111 {"mf", M0, OpX3X4X2 (0, 0, 2, 2), {}, EMPTY},
112 {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2), {}, EMPTY},
113 {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3), {}, EMPTY},
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dmove2.s78 R4 = M0;
96 P4 = M0;
116 A0.X = M0;
141 M0 = R0; define
145 M0 = A0.X; define
172 I1 = M0;
176 M0 = I1; define
177 M1 = M0;
182 B1 = M0;
187 L1 = M0;
Dmove2.d64 70: a4 30 R4 = M0;
80 90: a4 32 P4 = M0;
96 b0: 84 38 A0.X = M0;
116 d8: 20 34 M0 = R0;
120 e0: 20 35 M0 = A0.X;
141 10a: 8c 34 I1 = M0;
144 110: a1 34 M0 = I1;
145 112: ac 34 M1 = M0;
149 11a: 8c 36 B1 = M0;
153 122: ac 36 L1 = M0;
Dparallel.d12 10: 0a ce 0a 08 R4 = EXTRACT \(R2, R1.L\) \(Z\) \|\| I2 -= M0 \|\| NOP;
34 68: 10 cc 3f 40 A0 = ABS A1 \|\| P3 = \[FP -0x3c\] \|\| R1 = \[I1 \+\+ M0\];
106 188: 04 ca e8 80 R3.H = R5.H \* R0.L \|\| R4 = B\[P0\] \(X\) \|\| \[I0 \+\+ M0\] = R0;
108 190: 14 ca 09 40 R0.H = R1.L \* R1.H \(M\) \|\| R4 = B\[P1\] \(X\) \|\| \[I0 \+\+ M0\] = R1;
110 198: 1c cb 3e 80 R1 = R7.H \* R6.L \(M, IS\) \|\| R4 = B\[P2\] \(X\) \|\| \[I0 \+\+ M0\] = R2;
112 1a0: 0c ca 02 41 R5 = R0.L \* R2.H \|\| R4 = B\[P3\] \(X\) \|\| \[I0 \+\+ M0\] = R3;
114 1a8: 1c ca b0 c0 R3 = R6.H \* R0.H \(M\) \|\| R4 = B\[P4\] \(Z\) \|\| \[I0 \+\+ M0\] = R4;
116 1b0: 63 c8 2f 02 A0 = R5.L \* R7.H \(W32\) \|\| R4 = B\[P5\] \(Z\) \|\| \[I0 \+\+ M0\] = R5;
118 1b8: 03 c8 00 04 A0 = R0.H \* R0.L \|\| R5 = B\[P0\] \(X\) \|\| \[I0 \+\+ M0\] = R6;
120 1c0: 83 c8 13 0a A0 \+= R2.L \* R3.H \(FU\) \|\| R5 = B\[P1\] \(Z\) \|\| \[I0 \+\+ M0\] = R7;
[all …]
Dparallel.s4 r4 = extract (r2, r1.L) (z) || I2 -= M0;
20 A0 = ABS A1 || P3 = [FP-60] || R1 = [I1++M0];
69 r3.H = r5.H * r0.L || r4 = b [p0] (x) || [I0++M0] = R0;
70 R0.H = r1.L * r1.H (M) || r4 = b [p1] (x) || [i0++M0] = R1;
71 r1 = r7.H * r6.L (M, is) || r4 = b [p2] (x) || [i0++M0] = R2;
76 a0 = r0.h * r0.l || r5 = b [p0] (x) || [i0++M0] =R6;
77 A0 += R2.L * r3.H (FU) || r5 = b [p1] (z) || [i0++M0]=R7;
Dstack2.s20 [--SP ] = M0;
77 M0= [ SP ++ ] ;
Dstack2.d14 c: 54 01 \[--SP\] = M0;
50 54: 14 01 M0 = \[SP\+\+\];
Dparallel2.d30 58: 09 cc 10 c0 A1.X = R2.L \|\| R0 = \[I0 \+\+ M0\] \|\| NOP;
44 90: 83 c9 00 38 R0.L = A0 \(IU\) \|\| R4 = \[I1 \+\+ M0\] \|\| NOP;
46 98: 27 c8 40 18 R1.H = A1 \(S2RND\) \|\| R0 = \[I2 \+\+ M0\] \|\| NOP;
54 b8: 47 c8 00 38 R0.H = A1, R0.L = A0 \(T\) \|\| R5 = \[I3 \+\+ M0\] \|\| NOP;
Dpseudo.s27 DBG M0;
Dloop_temps.s264 M0 = R0; define
273 R0 = (A0 += A1) || I2 += M0;
Dstore.d28 2c: 8f 9f \[I1 \+\+ M0\] = R7;
Dload.s72 R4 = [i3 ++ M0];
Dpseudo.d27 28: 14 f8 DBG M0;
Darithmetic.d70 8c: 73 9e I3 -= M0;
79 9e: e0 9e I0 \+= M0 \(BREV\);
Dload.d62 9c: 9c 9d R4 = \[I3 \+\+ M0\];
Darithmetic.s86 I3 -= M0;
Dvector2.d460 …710: 01 cc 94 88 R2 = R2 \+\|\+ R4, R4 = R2 -\|- R4 \(ASR\) \|\| I0 \+= M0 \(BREV\) \|\| R1 = \[I…
470 738: 8b c8 9a 2f R6 = \(A0 \+= R3.H \* R2.H\) \(FU\) \|\| I2 -= M0 \|\| NOP;
Dvector2.s652 R2 = R2 +|+ R4, R4 = R2 -|- R4 (ASR) || I0 += M0 (BREV) || R1 = [I0] ;
/toolchain/binutils/binutils-2.25/cpu/
Dfrv.opc293 /* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
294 /* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
328 /* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
329 /* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
360 /* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
361 /* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
393 /* FMLOW */ UNIT_FM01, /* Only F0,F1,M0,M1 units */
Depiphany.cpu1838 ;; 16 bits form exists for group zero ( M1 and M0 equals to zero ) only
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-bfin.texi219 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
/toolchain/binutils/binutils-2.25/gas/
DChangeLog-20092186 * config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-M0.
2187 * doc/c-arm.texi: Added codes for processors ARM Cortex-M0 and