| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | mips16-opc.c | 152 #define MOD_1 (WR_1|RD_1) macro
189 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
196 {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
201 {"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
233 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
240 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
260 {"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
262 {"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
263 {"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
264 {"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
[all …]
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| D | micromips-opc.c | 216 #define MOD_1 (WR_1|RD_1) macro
327 {"addiu", "ms,mt,mY", 0x4c01, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addiusp */
328 {"addiu", "mp,mt,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addius5 */
335 {"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 },
342 {"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },
343 {"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 },
915 {"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },
916 {"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 },
956 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 },
958 {"scd", "t,~(b)", 0x6000f000, 0xfc00f000, MOD_1|RD_3|SM, 0, I3, 0, 0 },
[all …]
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| D | mips-opc.c | 289 #define MOD_1 (WR_1|RD_1) macro
1291 {"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
1292 {"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
1293 {"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
1857 {"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 },
1858 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I2, 0, EE|I37 },
1860 {"scd", "t,+j(b)", 0x7c000027, 0xfc00007f, MOD_1|RD_3|SM, 0, I69, 0, 0 },
1861 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I3, 0, EE|I69 },
2000 {"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
2001 {"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
[all …]
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| D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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