| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | aarch64-tbl.h | 31 #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)} macro
1362 {"ext", 0x2e000000, 0xbfe0c400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
1755 …{"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS |…
1756 …{"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_AL…
1757 …{"sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIA…
1762 …{"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | …
1763 …{"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS …
1764 …{"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_AL…
1765 …{"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS |…
1766 …{"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_AL…
[all …]
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| /toolchain/binutils/binutils-2.25/gas/config/ |
| D | tc-rx.c | 2221 #define OP4(x) op[target_big_endian ? 3-x : x] in md_apply_fix() macro
2300 OP4(0) = val & 0xff; in md_apply_fix()
2301 OP4(1) = (val >> 8) & 0xff; in md_apply_fix()
2302 OP4(2) = (val >> 16) & 0xff; in md_apply_fix()
2303 OP4(3) = (val >> 24) & 0xff; in md_apply_fix()
2309 OP4(0) = val & 0xff; in md_apply_fix()
2310 OP4(1) = (val >> 8) & 0xff; in md_apply_fix()
2311 OP4(2) = (val >> 16) & 0xff; in md_apply_fix()
2312 OP4(3) = (val >> 24) & 0xff; in md_apply_fix()
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| /toolchain/binutils/binutils-2.25/include/opcode/ |
| D | h8300.h | 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ argument
553 …{CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTD…
555 …{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTD…
556 …{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTD…
557 …{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTD…
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ argument
571 …{CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISP…
573 …{CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISP…
574 …{CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISP…
575 …{CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISP…
[all …]
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| D | tic6x-opcode-table.h | 45 #define OP4(a, b, c, d) 4, { a, b, c, d } macro
652 OP4(ORREG1, OACST, OACST, OWREG1),
664 OP4(ORREG1, OACST, OACST, OWREG1),
1142 OP4(ORREG1, OACST, OACST, OWREG1),
1154 OP4(ORREG1, OHWCST16, OHWCST16, OWREG1),
1158 OP4(ORREG1, OHWCST24, OHWCST24, OWREG1),
1164 OP4(ORREG1, OACST, OACST, OWREG1),
1176 OP4(ORREG1, OHWCST16, OHWCST16, OWREG1),
1180 OP4(ORREG1, OHWCST24, OHWCST24, OWREG1),
1184 OP4(ORREG1, OACST, OHWCST31, OWREG1Z),
[all …]
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