| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | dlx-dis.c | 36 #define OPC(x) ((x >> 26) & 0x3F) macro
106 unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */ in dlx_r_type()
193 { OPC(LHIOP), "lhi" }, /* Load HI to register. */ in dlx_load_type()
194 { OPC(LBOP), "lb" }, /* load byte sign extended. */ in dlx_load_type()
195 { OPC(LBUOP), "lbu" }, /* load byte unsigned. */ in dlx_load_type()
196 { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */ in dlx_load_type()
197 { OPC(LHOP), "lh" }, /* load halfword sign extended. */ in dlx_load_type()
198 { OPC(LHUOP), "lhu" }, /* load halfword unsigned. */ in dlx_load_type()
199 { OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */ in dlx_load_type()
200 { OPC(LWOP), "lw" }, /* load word. */ in dlx_load_type()
[all …]
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| D | cr16-opc.c | 29 #define ARITH_BYTE_INST(NAME, OPC, OP1) \ argument
31 {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{uimm4_1,20}, {regr,16}}}, \
33 {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}, \
35 {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
38 #define ARITH1_BYTE_INST(NAME, OPC, OP1) \ argument
40 {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}
79 #define ARITH_BYTE_INST1(NAME, OPC) \ argument
81 {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
87 #define ARITH_BYTE_INST2(NAME, OPC) \ argument
89 {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regp,16}}}
[all …]
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| D | crx-opc.c | 31 #define ARITH_BYTE_INST(NAME, OPC) \ argument
33 {NAME, 1, OPC, 24, ARITH_BYTE_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \
35 {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS | CST4MAP, {{i16,0}, {regr,16}}}, \
37 {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
64 #define ARITH_INST(NAME, OPC) \ argument
66 {NAME, 1, OPC, 24, ARITH_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \
68 {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS | CST4MAP, {{i16,0}, {regr,16}}}, \
70 {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0}, {regr,16}}}, \
72 {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}}
108 #define BRANCH_INST(NAME, OPC) \ argument
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| D | cgen.sh | 105 -OPC ${opcfile} \
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| /toolchain/binutils/binutils-2.25/gas/config/ |
| D | rx-parse.y | 1001 #define OPC(x) { #x, x, IS_OPCODE } macro
1002 OPC(ABS),
1003 OPC(ADC),
1004 OPC(ADD),
1006 OPC(BCLR),
1007 OPC(BCND),
1008 OPC(BMCND),
1009 OPC(BNOT),
1010 OPC(BRA),
1011 OPC(BRK),
[all …]
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| D | rl78-parse.y | 1256 #define OPC(x) { #x, x, IS_OPCODE } macro
1258 OPC(ADD),
1259 OPC(ADDC),
1260 OPC(ADDW),
1262 OPC(AND1),
1263 OPC(BC),
1264 OPC(BF),
1265 OPC(BH),
1266 OPC(BNC),
1267 OPC(BNH),
[all …]
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| D | tc-arm.c | 12925 #define X(OPC,I,F,S) N_MNEM_##OPC argument
12932 #define X(OPC,I,F,S) { (I), (F), (S) } argument
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| /toolchain/binutils/binutils-2.25/include/opcode/ |
| D | crx.h | 400 #define BIN(OPC,SHIFT) (OPC << SHIFT) argument
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| D | cr16.h | 414 #define BIN(OPC,SHIFT) (OPC << SHIFT) argument
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| D | aarch64.h | 72 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ argument
73 (((OPC) & (FEAT)) != 0)
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| /toolchain/binutils/binutils-2.25/bfd/ |
| D | xtensa-isa.c | 648 #define CHECK_OPCODE(INTISA,OPC,ERRVAL) \ argument
650 if ((OPC) < 0 || (OPC) >= (INTISA)->num_opcodes) \
860 #define CHECK_OPERAND(INTISA,OPC,ICLASS,OPND,ERRVAL) \ argument
867 (INTISA)->opcodes[(OPC)].name, (ICLASS)->num_operands); \
1259 #define CHECK_STATE_OPERAND(INTISA,OPC,ICLASS,STOP,ERRVAL) \ argument
1266 (INTISA)->opcodes[(OPC)].name, (ICLASS)->num_stateOperands); \
1306 #define CHECK_INTERFACE_OPERAND(INTISA,OPC,ICLASS,IFOP,ERRVAL) \ argument
1313 (INTISA)->opcodes[(OPC)].name, \
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| /toolchain/binutils/binutils-2.25/binutils/po/ |
| D | es.po | 4236 " -P, --private=OPC,OPC... Muestra contenidos específicos del formato objeto\n"
4312 " -M, --disassembler-options=OPC Pasa el texto OPC al desensamblador\n"
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