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Searched refs:O_JSR (Results 1 – 3 of 3) sorted by relevance

/toolchain/binutils/binutils-2.25/opcodes/
Dh8500-opc.h73 #define O_JSR 45 macro
968 {109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND,0},2, {{0x11,0xff,0 },{0xd8,0xf8,RD }}},
969 {109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{ABS16,0},3, {{0x18,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x0…
970 {109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D8,0},3, {{0x11,0xff,0 },{0xe8,0xf8,RDIND_D8 },{0x…
971 {109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D16,0},4, {{0x11,0xff,0 },{0xf8,0xf8,RDIND_D16 },{…
2083 {109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND,0},2, {{0x11,0xff,0},{0xd8,0xf8,RD }}},
2085 {109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D8,0},3, {{0x11,0xff,0},{0xe8,0xf8,RDIND_D8 },{0x0…
2087 {109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D16,0},4, {{0x11,0xff,0},{0xf8,0xf8,RDIND_D16 },{0…
2088 {109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{ABS16,0},3, {{0x18,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00…
/toolchain/binutils/binutils-2.25/include/opcode/
Dh8300.h1137 O_JSR, enumerator
1414 {O (O_JSR, SN), AV_H8, 6, "jsr", {{RSIND, E}}, {{0x5, 0xD, B30 | RSIND, 0x0, E}}},
1415 …{O (O_JSR, SN), AV_H8, 8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E…
1417 …{O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA…
1419 {O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}},
1420 {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
DChangeLog2050 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX