Searched refs:P5 (Results 1 – 25 of 36) sorted by relevance
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
D | control_code2.s | 73 CC = P5 == P0; 74 CC = P5 == P1; 76 CC = P3 == P5; 79 CC = P5 == -4; 80 CC = P5 == 0; 81 CC = P5 == 3; 87 CC = P5 < P0; 88 CC = P5 < P1; 90 CC = P3 < P5; 93 CC = P5 < -4; [all …]
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D | control_code2.d | 50 56: 45 08 CC = P5 == P0; 51 58: 4d 08 CC = P5 == P1; 53 5c: 6b 08 CC = P3 == P5; 54 5e: 65 0c CC = P5 == -0x4; 55 60: 45 0c CC = P5 == 0x0; 56 62: 5d 0c CC = P5 == 0x3; 60 6a: c5 08 CC = P5 < P0; 61 6c: cd 08 CC = P5 < P1; 63 70: eb 08 CC = P3 < P5; 64 72: e5 0c CC = P5 < -0x4; [all …]
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D | cache2.s | 15 PREFETCH [ P5 ] ; 25 PREFETCH [ P5++ ] ; 35 FLUSH [ P5 ] ; 44 FLUSH [ P5++ ] ; 54 FLUSHINV [ P5 ] ; 64 FLUSHINV [ P5++ ] ; 74 IFLUSH [ P5 ] ; 84 IFLUSH [ P5++ ] ;
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D | cache2.d | 12 a: 45 02 PREFETCH\[P5\]; 20 1a: 65 02 PREFETCH\[P5\+\+\]; 28 2a: 55 02 FLUSH\[P5\]; 36 3a: 75 02 FLUSH\[P5\+\+\]; 44 4a: 4d 02 FLUSHINV\[P5\]; 52 5a: 6d 02 FLUSHINV\[P5\+\+\]; 60 6a: 5d 02 IFLUSH\[P5\]; 68 7a: 7d 02 IFLUSH\[P5\+\+\];
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D | stack2.s | 56 [--SP ] = ( R7:0, P5:0); 63 [--SP ] = (P5:0); 112 ( R7:0, P5:0) = [ SP++ ]; 118 ( P5:0) = [ SP++ ]; 127 L$L$foo: (R7:6,P5:3) = [SP++]; /* Pop multiple on the same line with a label */
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D | stack.d | 17 10: d0 05 \[--SP\] = \(R7:2, P5:0\); 19 14: c2 04 \[--SP\] = \(P5:2\); 31 24: a8 05 \(R7:5, P5:0\) = \[SP\+\+\]; 33 28: 84 04 \(P5:4\) = \[SP\+\+\];
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D | stack2.d | 41 42: c0 05 \[--SP\] = \(R7:0, P5:0\); 43 46: c0 04 \[--SP\] = \(P5:0\); 77 8a: 80 05 \(R7:0, P5:0\) = \[SP\+\+\]; 79 8e: 80 04 \(P5:0\) = \[SP\+\+\]; 84 a0: b3 05 \(R7:6, P5:3\) = \[SP\+\+\];
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D | move2.s | 24 P5 = P5; define 40 R6 = P5; 48 P5 = R6; define 97 P5 = M1; define 106 P5 = L1; define 248 RETX =P5; 256 LB0 = P5; 329 IF CC P4 = P5; 331 IF CC P5 = P4; 335 IF CC P5 = R7; [all …]
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D | flow2.s | 18 JUMP (P5); 28 JUMP (PC+P5); 104 CALL(P5); 113 CALL(PC+P5);
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D | move2.d | 21 1a: 6d 32 P5 = P5; 34 34: 75 30 R6 = P5; 41 42: 2e 32 P5 = R6; 81 92: ad 32 P5 = M1; 89 a2: ed 32 P5 = L1; 204 188: 65 3e RETX = P5; 212 198: 55 3c LB0 = P5; 244 200: e5 07 IF CC P4 = P5; 246 204: ec 07 IF CC P5 = P4; 249 20a: af 07 IF CC P5 = R7; [all …]
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D | store.s | 6 [fp --] = P5; 8 [P5 + 131068] = P0; 17 [P5 ++] = R2;
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D | flow.s | 8 jump(P5); 79 LSETUP(30, 1024) LC0 = P5; 90 LSETUP (30, 1024) LC1 = P5;
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D | store.d | 9 4: fd 92 \[FP--\] = P5; 11 8: 28 e7 ff 7f \[P5 \+ 0x1fffc\] = P0; 18 14: 2a 92 \[P5\+\+\] = R2;
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D | flow2.d | 13 a: 55 00 JUMP \(P5\); 21 1a: 85 00 JUMP \(PC \+ P5\); 69 84: 65 00 CALL \(P5\); 75 90: 75 00 CALL \(PC \+ P5\);
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D | stack.s | 34 (R7:5, P5:0) = [sp++]; 36 (P5:4) = [Sp++];
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D | load.d | 13 14: 4d e1 20 00 P5.H = 0x20;.* 47 7e: 0d b8 P5 = \[FP -0x80\]; 51 82: 2e 90 R6 = \[P5\+\+\]; 71 ae: 28 86 R0 = W\[P0 \+\+ P5\] \(Z\);
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D | flow.d | 8 0: 55 00 JUMP \(P5\); 61 78: af e0 00 52 LSETUP\(0x76 <loop_lc0\+0x36>, 0xfffffc78 <loop_lc1\+0xfffffbf8>\) LC0 = P5; 69 90: bf e0 00 52 LSETUP\(0x8e <loop_lc1\+0xe>, 0xfffffc90 <loop_lc1\+0xfffffc10>\) LC1 = P5;
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D | parallel3.d | 70 f8: 01 ce 11 88 R4 = LSHIFT R1 BY R2.L \(V\) \|\| \[P5\] = P0 \|\| NOP; 72 100: 06 cc 01 0c R6 = MAX \(R0, R1\) \(V\) \|\| \[P5\+\+\] = P0 \|\| NOP; 74 108: 06 cc 17 40 R0 = MIN \(R2, R7\) \(V\) \|\| \[P5--\] = P0 \|\| NOP; 76 110: 04 ca be 66 R2.H = R7.L \* R6.H, R2.L = R7.H \* R6.H \|\| \[P5 \+ 0x8\] = P0 \|\| NOP; 78 118: 04 ca 08 e1 R4.H = R1.H \* R0.H, R4.L = R1.L \* R0.L \|\| \[P5 \+ 0x4\] = P0 \|\| NOP; 80 120: 04 ca 1a a0 R0.H = R3.H \* R2.L, R0.L = R3.L \* R2.L \|\| \[P5\] = P0 \|\| NOP; 108 190: 04 c8 d1 c9 R7.H = \(A1 = R2.H \* R1.H\), A0 \+= R2.L \* R1.L \|\| \[P0\] = P5 \|\| NOP;
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D | parallel4.d | 62 d8: 12 cc 02 20 SAA \(R1:0, R3:2\) \(R\) \|\| \[P5\] = R0 \|\| NOP; 64 e0: 18 cc c0 45 \(R7, R2\) = BYTEUNPACK R1:0 \|\| \[P5\+\+\] = R0 \|\| NOP; 66 e8: 18 cc 90 69 \(R6, R4\) = BYTEUNPACK R3:2 \(R\) \|\| \[P5--\] = R0 \|\| NOP;
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D | shift.d | 9 2: ea 45 P2 = \(P2 \+ P5\) << 0x2; 14 8: 44 5f P5 = P4 \+ \(P0 << 0x2\); 43 5a: 6c 44 P4 = P5 << 0x2;
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D | parallel2.s | 77 A0 = ROT A0 by r7.l || R5 = W [P5] (z); 78 A1 = rot a1 bY r6.l || R5 = W [P5++] (z); 80 NOp || R5 = W [P5--] (z);
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D | load.s | 54 P5 = [FP-128]; define 83 R0 = W [ P0 ++ P5] (z);
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D | parallel2.d | 10 8: 08 cc 3f e0 A1 = A0 \|\| P0 = \[P5 \+ 0x18\] \|\| NOP; 142 218: 03 ce 38 80 A0 = ROT A0 BY R7.L \|\| R5 = W\[P5\] \(Z\) \|\| NOP; 144 220: 03 ce 30 90 A1 = ROT A1 BY R6.L \|\| R5 = W\[P5\+\+\] \(Z\) \|\| NOP; 146 228: 03 c8 00 18 MNOP \|\| R5 = W\[P5--\] \(Z\) \|\| NOP;
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D | parallel.d | 30 58: 06 ce 02 ce R7.L = ONES R2 \|\| P1 = \[P5 \+ 0x18\] \|\| NOP; 40 80: 10 cc 3f c0 A1 = ABS A1, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\]; 68 f0: 07 ce 2b 48 R4.L = EXPADJ \(R3, R5.L\) \(V\) \|\| R1 = B\[P5\] \(Z\) \|\| W\[I0\+\+\] = R1.L; 80 120: 0b cc 3f e0 A0 -= A1 \(W32\) \|\| B\[P5\] = R2 \|\| R3 = \[I1\+\+\]; 100 170: 08 cb 0b 20 R0 = R1.L \* R3.L \(IS\) \|\| B\[P5\] = R3 \|\| R5 = \[I0\+\+\]; 116 1b0: 63 c8 2f 02 A0 = R5.L \* R7.H \(W32\) \|\| R4 = B\[P5\] \(Z\) \|\| \[I0 \+\+ M0\] = R5; 128 1e0: 10 c8 08 58 A1 = R1.L \* R0.H \(M\) \|\| R5 = B\[P5\] \(X\) \|\| \[I1 \+\+ M1\] = R4;
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D | cache.d | 7 0: 45 02 PREFETCH\[P5\];
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