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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic4x/
Dopcodes.s408 … absf R1, R0 & absf R0 & absf @start, R0 & abs…
409 …R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf *+AR0(1), R0 & .endi…
411 …R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi *+AR0(1), R0 & .endi…
414 … addf R1, R0 & addf R0 & addf @start, R0 & add…
415 …R0 & addf R1, R0 & addf R1, *+AR0(1), R0 …
416 …R0 &|| stf R1, *+AR1(1) & addf *+AR0(1), R0 &|| stf R1, *+AR…
419 …R0 &|| sti R1, *+AR1(1) & addi *+AR0(1), R0 &|| sti R1, *+AR…
422 …R0 &|| sti R1, *+AR1(1) & and *+AR0(1), R0 &|| sti R1, *+AR1…
427 …R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash…
428 … & bC R0 & bC start & b_J: …
[all …]
Daddressing.s43 Type_CI:ldiu R0,R0 ; Unconditional load (00000)
44 ldic R0,R0 ; Carry load (00001)
45 ldilo R0,R0 ; Lower than load (00001)
46 ldils R0,R0 ; Lower than or same load (00010)
47 ldihi R0,R0 ; Higher than load (00011)
48 ldihs R0,R0 ; Higher than or same load (00100)
49 ldinc R0,R0 ; No carry load (00100)
50 ldieq R0,R0 ; Equal to load (00101)
51 ldiz R0,R0 ; Zero load (00101)
52 ldine R0,R0 ; Not equal to load (00110)
[all …]
Dopclasses.h110 name R1, R0 /* q;R */ &\
111 name R0 /* q;R */ &\
202 name R1, R0 /* q;r */ &\
203 name R0 /* q;r */ &\
204 name @start, R0 /* @,r */ &\
205 name *+AR0(5), R0 /* *,r */ &\
206 name 3.5, R0 /* F,r */ &\
219 name AR1, R0 /* Q;r */ &\
220 name R0 /* Q;r */ &\
221 name @start, R0 /* @,r */ &\
[all …]
Dregisters.s5 start: ldi R0,R0
6 ldi R0,R1
7 ldi R0,R2
8 ldi R0,R3
9 ldi R0,R4
10 ldi R0,R5
11 ldi R0,R6
12 ldi R0,R7
13 ldi R0,AR0
14 ldi R0,AR1
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mt/
Dallinsn.d10 0: 00 00 00 00 add R0,R0,R0
13 4: 02 00 00 00 addu R0,R0,R0
16 8: 01 00 00 00 addi R0,R0,#\$0
19 c: 03 00 00 00 addui R0,R0,#\$0
22 10: 04 00 00 00 sub R0,R0,R0
25 14: 06 00 00 00 subu R0,R0,R0
28 18: 05 00 00 00 subi R0,R0,#\$0
31 1c: 07 00 00 00 subui R0,R0,#\$0
34 20: 10 00 00 00 and R0,R0,R0
37 24: 11 00 00 00 andi R0,R0,#\$0
[all …]
Dallinsn.s8 add R0,R0,R0
12 addu R0,R0,R0
16 addi R0,R0,#0
20 addui R0,R0,#0
24 sub R0,R0,R0
28 subu R0,R0,R0
32 subi R0,R0,#0
36 subui R0,R0,#0
40 and R0,R0,R0
44 andi R0,R0,#0
[all …]
Dmsys.d10 0: 80 00 00 00 ldctxt R0,R0,#\$0,#\$0,#\$0
11 4: 84 00 00 00 ldfb R0,R0,#\$0
12 8: 88 00 00 00 stfb R0,R0,#\$0
13 c: 8c 00 00 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
14 10: 90 00 00 00 mfbcb R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0
15 14: 94 00 00 00 fbcci R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
16 18: 98 00 00 00 fbrci R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
17 1c: 9c 00 00 00 fbcri R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
18 20: a0 00 00 00 fbrri R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
19 24: a4 00 00 00 mfbcci R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
[all …]
Dmsys.s3 ; Make sure that each mnemonic gives the proper opcode. Use R0 and #0
7 ldctxt R0,R0,#0,#0,#0
8 ldfb R0,R0,#0
9 stfb R0, R0, #0
10 fbcb R0,#0,#0,#0,#0,#0,#0,#0,#0
11 mfbcb R0,#0,R0,#0,#0,#0,#0,#0
12 fbcci R0,#0,#0,#0,#0,#0,#0,#0
13 fbrci R0,#0,#0,#0,#0,#0,#0,#0
14 fbcri R0,#0,#0,#0,#0,#0,#0,#0
15 fbrri R0,#0,#0,#0,#0,#0,#0,#0
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dloop_temps.s12 [FP+28] = R0;
16 R0 = SP; define
17 [FP+-24] = R0;
18 R0 = [FP+44]; define
19 R3 = R0;
22 R0 = R2; define
25 R0 = R0 & R2; define
28 R2 = R0 >> 27;
34 R2 = R0 << 5;
36 R0 = [FP+-64]; define
[all …]
Dshift2.d16 10: 00 41 R0 = \(R0 \+ R0\) << 0x1;
17 12: 08 41 R0 = \(R0 \+ R1\) << 0x1;
18 14: 02 41 R2 = \(R2 \+ R0\) << 0x1;
20 18: 40 41 R0 = \(R0 \+ R0\) << 0x2;
21 1a: 48 41 R0 = \(R0 \+ R1\) << 0x2;
22 1c: 42 41 R2 = \(R2 \+ R0\) << 0x2;
44 48: 00 4d R0 >>>= 0x0;
45 4a: f8 4d R0 >>>= 0x1f;
46 4c: 28 4d R0 >>>= 0x5;
50 54: 00 4f R0 <<= 0x0;
[all …]
Dshift2.s26 R0 = (R0+R0)<<1; define
27 R0 = (R0+R1)<<1; define
28 R2 = (R2+R0)<<1;
35 R0 = (R0+R0)<<2; define
36 R0 = (R0+R1)<<2; define
37 R2 = (R2+R0)<<2;
67 R0 >>>= 0; label
68 R0 >>>= 31; label
69 R0 >>>= 5; label
75 R0 <<= 0; label
[all …]
Darith_mode.s5 R0.L = A0;
6 R0.L = A0 (FU);
7 R0.L = A0 (IS);
8 R0.L = A0 (IU);
9 R0.L = A0 (T);
10 R0.L = A0 (TFU); // Not documented
11 R0.L = A0 (S2RND);
12 R0.L = A0 (ISS2);
13 R0.L = A0 (IH);
17 R0 = A0; define
[all …]
Darith_mode.d9 0: 03 c0 00 38 R0.L = A0;
10 4: 83 c0 00 38 R0.L = A0 \(FU\);
11 8: 03 c1 00 38 R0.L = A0 \(IS\);
12 c: 83 c1 00 38 R0.L = A0 \(IU\);
13 10: 43 c0 00 38 R0.L = A0 \(T\);
14 14: c3 c0 00 38 R0.L = A0 \(TFU\);
15 18: 23 c0 00 38 R0.L = A0 \(S2RND\);
16 1c: 23 c1 00 38 R0.L = A0 \(ISS2\);
17 20: 63 c1 00 38 R0.L = A0 \(IH\);
18 24: 0b c0 00 38 R0 = A0;
[all …]
Dmove2.s10 R0 = R0; define
34 R0 = A1.W; define
55 A1.W = R0;
74 R0 = I0; define
83 R0 = B0; define
132 I0 = R0;
141 M0 = R0;
150 B0 = R0;
159 L0 = R0;
208 R0 = ASTAT; define
[all …]
Dparallel4.d8 0: 0d ce 15 0e R7 = ALIGN8 \(R5, R2\) \|\| \[I0\] = R0 \|\| NOP;
10 8: 0d ce 08 4a R5 = ALIGN16 \(R0, R1\) \|\| \[I0\+\+\] = R0 \|\| NOP;
12 10: 0d ce 05 84 R2 = ALIGN24 \(R5, R0\) \|\| \[I0--\] = R0 \|\| NOP;
14 18: 12 cc 00 c0 DISALGNEXCPT \|\| \[I1\] = R0 \|\| NOP;
16 20: 17 cc 02 0a R5 = BYTEOP3P \(R1:0, R3:2\) \(LO\) \|\| \[I1\+\+\] = R0 \|\| NOP;
18 28: 37 cc 02 00 R0 = BYTEOP3P \(R1:0, R3:2\) \(HI\) \|\| \[I1--\] = R0 \|\| NOP;
20 30: 17 cc 02 22 R1 = BYTEOP3P \(R1:0, R3:2\) \(LO, R\) \|\| \[I2\] = R0 \|\| NOP;
22 38: 37 cc 02 24 R2 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\) \|\| \[I2\+\+\] = R0 \|\| NOP;
24 40: 0c cc 7f 45 R5 = A1.L \+ A1.H, R2 = A0.L \+ A0.H \|\| \[I2--\] = R0 \|\| NOP;
26 48: 15 cc 82 06 \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\) \|\| \[I3\] = R0 \|\| NOP;
[all …]
Dvector2.d9 4: 0c c4 0a 00 R0.H = R0.L = SIGN \(R1.H\) \* R2.H \+ SIGN \(R1.L\) \* R2.L;
11 c: 0c c4 38 0c R6.H = R6.L = SIGN \(R7.H\) \* R0.H \+ SIGN \(R7.L\) \* R0.L;
14 18: 0c c4 01 0e R7.H = R7.L = SIGN \(R0.H\) \* R1.H \+ SIGN \(R0.L\) \* R1.L;
17 24: 09 c6 01 ce R7 = VIT_MAX \(R1, R0\) \(ASR\);
18 28: 09 c6 11 80 R0 = VIT_MAX \(R1, R2\) \(ASL\);
20 30: 09 c6 07 8c R6 = VIT_MAX \(R7, R0\) \(ASL\);
23 3c: 09 c6 08 ce R7 = VIT_MAX \(R0, R1\) \(ASR\);
28 50: 09 c6 01 00 R0.L = VIT_MAX \(R1\) \(ASL\);
35 6c: 09 c6 00 4e R7.L = VIT_MAX \(R0\) \(ASR\);
37 74: 06 c4 00 80 R0 = ABS R0 \(V\);
[all …]
Dmove2.d8 0: 00 30 R0 = R0;
28 28: 03 31 R0 = A1.W;
47 4e: 18 38 A1.W = R0;
60 68: 80 30 R0 = I0;
68 78: c0 30 R0 = B0;
108 c8: 00 34 I0 = R0;
116 d8: 20 34 M0 = R0;
124 e8: 00 36 B0 = R0;
132 f8: 20 36 L0 = R0;
168 140: 06 31 R0 = ASTAT;
[all …]
Dexpected_errors.s15 R1.H = (A1=R7.L*R5.L) , A0 += R1.L*R0.L (IS);
23 R0.H = (A1 = R4.L * R3.L) (T), A0 = R4.H * R3.L;
24 R0.L = (A0 = R7.L * R4.H) (T), A1 += R7.H * R4.H;
26 R0 = (A1 += R1.H * R3.H) (IU) define
27 R0.L = (A1 += R1.H * R3.H) (IU)
57 [ R0 ++ M2 ] = R2;
59 [ R0 ++ P2 ] = R2;
64 W [ R0 ++ M2 ] = R2.h;
66 W [ R0 ++ P2 ] = R2.h;
71 [ R0 ++ ] = R2;
[all …]
Dlogical2.s12 R7 = R7 & R0;
16 R2 = R7 & R0;
22 R7 = ~R0;
23 R0 = ~R7; define
24 R0 = ~R2; define
30 R7 = R7 | R0;
34 R3 = R7 | R0;
40 R7 = R7 ^ R0;
44 R3 = R7 ^ R0;
47 R0.L = CC = BXORSHIFT(A0, R0);
[all …]
Dparallel2.d12 10: 09 cc 00 20 A0 = R0 \|\| P0 = \[P4 \+ 0x1c\] \|\| NOP;
26 48: 8f c8 00 38 R1 = A1, R0 = A0 \(FU\) \|\| P0 = \[P4 \+ 0x38\] \|\| NOP;
30 58: 09 cc 10 c0 A1.X = R2.L \|\| R0 = \[I0 \+\+ M0\] \|\| NOP;
32 60: 0a cc 3f 00 R0.L = A0.X \|\| R1 = \[I0 \+\+ M1\] \|\| NOP;
34 68: 0a cc 3f 4e R7.L = A1.X \|\| R0 = \[I0 \+\+ M2\] \|\| NOP;
36 70: 09 cc 18 00 A0.L = R3.L \|\| R0 = \[I0 \+\+ M3\] \|\| NOP;
38 78: 09 cc 20 80 A1.L = R4.L \|\| R0 = \[I1 \+\+ M3\] \|\| NOP;
40 80: 29 cc 30 00 A0.H = R6.H \|\| R0 = \[I1 \+\+ M2\] \|\| NOP;
42 88: 29 cc 28 80 A1.H = R5.H \|\| R0 = \[I1 \+\+ M1\] \|\| NOP;
44 90: 83 c9 00 38 R0.L = A0 \(IU\) \|\| R4 = \[I1 \+\+ M0\] \|\| NOP;
[all …]
Dflow.s55 R0 = [FP+-3604]; define
57 R0 = [FP+-3604]; define
58 P0 = R0;
61 R0 = -1200 (X); define
62 P1 = R0;
64 R0 = 0 (X); define
65 [P2] = R0;
66 R0 = [FP+-3604]; define
67 R0 += 1;
68 [FP+-3604] = R0;
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/epiphany/
Dregression.s28 START: MOV R0, #TABLE ; //Setting R0 to TABLE
29 LSL R0,R0,#2 ; //Create 00020000
84 NEXT: STRB R4,[R0,#0x0] ;//Store Byte
85 LDRB R63,[R0,#0x0] ;//Load Byte
88 STOREB: STRB R5,[R0,#0xf] ;//Store Byte
89 LDRB R63,[R0,#0xf] ;//Load Byte
92 STORES: STRH R4,[R0,#0x0] ;//Store Short
93 LDRH R63,[R0,#0x0] ;//Load Short
96 STORES2: STRH R5,[R0,#0xe] ;//Store Short
97 LDRH R63,[R0,#0xe] ;//Load Short
[all …]
/toolchain/binutils/binutils-2.25/opcodes/
Dlm32-opc.c154 { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } },
160 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } },
166 { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } },
172 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } },
178 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (HI16), 0 } },
184 { { MNEM, ' ', OP (R0), 0 } },
196 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
202 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
208 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
214 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dneon-addressing-bad.s5 VLD1.8 {D0}, R0
6 VLD1.8 {Q1}, R0
9 VST1.8 {D0}, R0
10 VST1.8 {Q1}, R0
13 VST1.8 {D0[]}, [R0]
14 VST2.8 {D0[], D2[]}, [R0]
15 VST3.16 {D0[], D1[], D2[]}, [R0]
16 VST4.32 {D0[], D1[], D2[], D3[]}, [R0]
17 VLD1.8 {Q0}, [R0, #8]
18 VLD1.8 {Q0}, [R0, #8]!
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/z8k/
Dctrl-names.s20 LDCTL R0,FCW
21 LDCTL FCW,R0
22 LDCTL R0,REFRESH
23 LDCTL REFRESH,R0
24 LDCTL R0,PSAPSEG
25 LDCTL PSAPSEG,R0
26 LDCTL R0,PSAPOFF
27 LDCTL PSAPOFF,R0
28 LDCTL R0,PSAP
29 LDCTL PSAP,R0
[all …]

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