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Searched refs:R1 (Results 1 – 25 of 123) sorted by relevance

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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dvideo2.d9 [ 0-9a-f]+: 0d c6 08 00 R0 = ALIGN8 \(R0, R1\);
10 [ 0-9a-f]+: 0d c6 01 00 R0 = ALIGN8 \(R1, R0\);
11 [ 0-9a-f]+: 0d c6 09 00 R0 = ALIGN8 \(R1, R1\);
12 [ 0-9a-f]+: 0d c6 11 00 R0 = ALIGN8 \(R1, R2\);
15 [ 0-9a-f]+: 0d c6 1a 02 R1 = ALIGN8 \(R2, R3\);
17 [ 0-9a-f]+: 0d c6 08 0e R7 = ALIGN8 \(R0, R1\);
21 [ 0-9a-f]+: 0d c6 08 40 R0 = ALIGN16 \(R0, R1\);
22 [ 0-9a-f]+: 0d c6 01 40 R0 = ALIGN16 \(R1, R0\);
23 [ 0-9a-f]+: 0d c6 09 40 R0 = ALIGN16 \(R1, R1\);
24 [ 0-9a-f]+: 0d c6 11 40 R0 = ALIGN16 \(R1, R2\);
[all …]
Dloop_temps.s13 [FP+32] = R1;
23 R1 = 0 (X); define
27 R1 = R1 & R2; define
29 R7 = R1 << 5;
37 R1 = [FP+-60]; define
39 [FP+-60] = R1;
41 R1 = [FP+-64]; define
42 R1 = R1 & R0; define
43 [FP+-64] = R1;
49 R1 = 0 (X); define
[all …]
Darith_mode.s26 R0.H = R1.L * R2.H;
27 R0.H = R1.L * R2.H (FU);
28 R0.H = R1.L * R2.H (IS);
29 R0.H = R1.L * R2.H (IU);
30 R0.H = R1.L * R2.H (T);
31 R0.H = R1.L * R2.H (TFU);
32 R0.H = R1.L * R2.H (S2RND);
33 R0.H = R1.L * R2.H (ISS2);
34 R0.H = R1.L * R2.H (IH);
38 R0 = R1.L * R2.H;
[all …]
Dbit2.s13 BITCLR ( R1 , 0 ) ;
21 BITSET ( R1 , 0 ) ;
29 BITTGL ( R1 , 0 ) ;
37 CC = BITTST ( R1 , 0 ) ;
45 CC = !BITTST ( R1 , 0 ) ;
50 R7 = DEPOSIT(R0, R1);
51 R7 = DEPOSIT(R7, R1);
53 R1 = DEPOSIT(R0, R1); define
54 R2 = DEPOSIT(R7, R1);
58 R7 = DEPOSIT(R0, R1)(X);
[all …]
Dmove2.s11 R1 = R1; define
35 R1 = A1.X; define
54 A1.X = R1;
75 R1 = I1; define
84 R1 = B1; define
192 R1 = USP; define
209 R1 = SEQSTAT; define
217 R1 = LC1; define
227 SEQSTAT = R1;
234 LC0 = R1;
[all …]
Dshift2.d17 12: 08 41 R0 = \(R0 \+ R1\) << 0x1;
19 16: 11 41 R1 = \(R1 \+ R2\) << 0x1;
21 1a: 48 41 R0 = \(R0 \+ R1\) << 0x2;
23 1e: 51 41 R1 = \(R1 \+ R2\) << 0x2;
64 80: 80 c6 01 00 R0.L = R1.L >>> 0x0;
65 84: 80 c6 89 01 R0.L = R1.L >>> 0xf;
66 88: 80 c6 01 10 R0.L = R1.H >>> 0x0;
67 8c: 80 c6 89 11 R0.L = R1.H >>> 0xf;
68 90: 80 c6 01 20 R0.H = R1.L >>> 0x0;
69 94: 80 c6 89 21 R0.H = R1.L >>> 0xf;
[all …]
Darith_mode.d24 3c: 04 c2 0a 40 R0.H = R1.L \* R2.H;
25 40: 84 c2 0a 40 R0.H = R1.L \* R2.H \(FU\);
26 44: 04 c3 0a 40 R0.H = R1.L \* R2.H \(IS\);
27 48: 84 c3 0a 40 R0.H = R1.L \* R2.H \(IU\);
28 4c: 44 c2 0a 40 R0.H = R1.L \* R2.H \(T\);
29 50: c4 c2 0a 40 R0.H = R1.L \* R2.H \(TFU\);
30 54: 24 c2 0a 40 R0.H = R1.L \* R2.H \(S2RND\);
31 58: 24 c3 0a 40 R0.H = R1.L \* R2.H \(ISS2\);
32 5c: 64 c3 0a 40 R0.H = R1.L \* R2.H \(IH\);
33 60: 08 c2 0a 22 R0 = R1.L \* R2.H;
[all …]
Dbit2.d11 6: 01 4c BITCLR \(R1, 0x0\);.*
17 12: 01 4a BITSET \(R1, 0x0\);.*
23 1e: 01 4b BITTGL \(R1, 0x0\);.*
29 2a: 01 49 CC = BITTST \(R1, 0x0\);.*
35 36: 01 48 CC = !BITTST \(R1, 0x0\);.*
38 3c: 0a c6 08 8e R7 = DEPOSIT \(R0, R1\);
39 40: 0a c6 0f 8e R7 = DEPOSIT \(R7, R1\);
41 48: 0a c6 08 82 R1 = DEPOSIT \(R0, R1\);
42 4c: 0a c6 0f 84 R2 = DEPOSIT \(R7, R1\);
44 54: 0a c6 08 ce R7 = DEPOSIT \(R0, R1\) \(X\);
[all …]
Dvector2.d9 4: 0c c4 0a 00 R0.H = R0.L = SIGN \(R1.H\) \* R2.H \+ SIGN \(R1.L\) \* R2.L;
12 10: 0c c4 13 02 R1.H = R1.L = SIGN \(R2.H\) \* R3.H \+ SIGN \(R2.L\) \* R3.L;
14 18: 0c c4 01 0e R7.H = R7.L = SIGN \(R0.H\) \* R1.H \+ SIGN \(R0.L\) \* R1.L;
17 24: 09 c6 01 ce R7 = VIT_MAX \(R1, R0\) \(ASR\);
18 28: 09 c6 11 80 R0 = VIT_MAX \(R1, R2\) \(ASL\);
21 34: 09 c6 1a c2 R1 = VIT_MAX \(R2, R3\) \(ASR\);
23 3c: 09 c6 08 ce R7 = VIT_MAX \(R0, R1\) \(ASR\);
26 48: 09 c6 01 06 R3.L = VIT_MAX \(R1\) \(ASL\);
27 4c: 09 c6 01 46 R3.L = VIT_MAX \(R1\) \(ASR\);
28 50: 09 c6 01 00 R0.L = VIT_MAX \(R1\) \(ASL\);
[all …]
Dvideo.d8 [ 0-9a-f]+: 0d c6 08 4a R5 = ALIGN16 \(R0, R1\);
15 [ 0-9a-f]+: 17 c4 02 0a R5 = BYTEOP3P \(R1:0, R3:2\) \(LO\);
16 [ 0-9a-f]+: 37 c4 02 00 R0 = BYTEOP3P \(R1:0, R3:2\) \(HI\);
17 [ 0-9a-f]+: 17 c4 02 22 R1 = BYTEOP3P \(R1:0, R3:2\) \(LO, R\);
18 [ 0-9a-f]+: 37 c4 02 24 R2 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\);
24 [ 0-9a-f]+: 15 c4 82 06 \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\);
25 [ 0-9a-f]+: 15 c4 82 21 \(R6, R0\) = BYTEOP16P \(R1:0, R3:2\) \(R\);
28 [ 0-9a-f]+: 14 c4 02 0e R7 = BYTEOP1P \(R1:0, R3:2\);
29 [ 0-9a-f]+: 14 c4 02 44 R2 = BYTEOP1P \(R1:0, R3:2\) \(T\);
30 [ 0-9a-f]+: 14 c4 02 26 R3 = BYTEOP1P \(R1:0, R3:2\) \(R\);
[all …]
Dmove2.d9 2: 09 30 R1 = R1;
29 2a: 0a 31 R1 = A1.X;
46 4c: 11 38 A1.X = R1;
61 6a: 89 30 R1 = I1;
69 7a: c9 30 R1 = B1;
156 128: c8 31 R1 = USP;
169 142: c9 31 R1 = SEQSTAT;
177 152: 8b 31 R1 = LC1;
185 162: 09 3e SEQSTAT = R1;
192 170: 01 3c LC0 = R1;
[all …]
Dinvalid_arith_mode.s18 R0.H = R1.L * R2.H (W32);
22 R0 = R1.L * R2.H (IU);
23 R0 = R1.L * R2.H (T);
24 R0 = R1.L * R2.H (TFU);
25 R0 = R1.L * R2.H (IH);
26 R0 = R1.L * R2.H (W32);
30 A0 = R1.L * R2.H (IU);
31 A0 = R1.L * R2.H (T);
32 A0 = R1.L * R2.H (TFU);
33 A0 = R1.L * R2.H (S2RND);
[all …]
Dparallel4.d10 8: 0d ce 08 4a R5 = ALIGN16 \(R0, R1\) \|\| \[I0\+\+\] = R0 \|\| NOP;
16 20: 17 cc 02 0a R5 = BYTEOP3P \(R1:0, R3:2\) \(LO\) \|\| \[I1\+\+\] = R0 \|\| NOP;
18 28: 37 cc 02 00 R0 = BYTEOP3P \(R1:0, R3:2\) \(HI\) \|\| \[I1--\] = R0 \|\| NOP;
20 30: 17 cc 02 22 R1 = BYTEOP3P \(R1:0, R3:2\) \(LO, R\) \|\| \[I2\] = R0 \|\| NOP;
22 38: 37 cc 02 24 R2 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\) \|\| \[I2\+\+\] = R0 \|\| NOP;
26 48: 15 cc 82 06 \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\) \|\| \[I3\] = R0 \|\| NOP;
28 50: 15 cc 82 21 \(R6, R0\) = BYTEOP16P \(R1:0, R3:2\) \(R\) \|\| \[I3\+\+\] = R0 \|\| NOP;
30 58: 14 cc 02 4e R7 = BYTEOP1P \(R1:0, R3:2\) \(T\) \|\| \[I3--\] = R0 \|\| NOP;
32 60: 14 cc 02 44 R2 = BYTEOP1P \(R1:0, R3:2\) \(T\) \|\| \[P0\] = R0 \|\| NOP;
34 68: 14 cc 02 26 R3 = BYTEOP1P \(R1:0, R3:2\) \(R\) \|\| \[P0\+\+\] = R0 \|\| NOP;
[all …]
Dshift2.s27 R0 = (R0+R1)<<1;
29 R1 = (R1+R2)<<1; define
36 R0 = (R0+R1)<<2;
38 R1 = (R1+R2)<<2; define
91 R0.L = R1.L >>> 0;
92 R0.L = R1.L >>> 15;
93 R0.L = R1.H >>> 0;
94 R0.L = R1.H >>> 15;
95 R0.H = R1.L >>> 0;
96 R0.H = R1.L >>> 15;
[all …]
Dexpected_errors.s15 R1.H = (A1=R7.L*R5.L) , A0 += R1.L*R0.L (IS);
26 R0 = (A1 += R1.H * R3.H) (IU)
27 R0.L = (A1 += R1.H * R3.H) (IU)
28 R1 = (A0 += R1.H * R3.H) (IU) define
29 R1.H = (A0 += R1.H * R3.H) (IU)
121 R0.L = A0, R1.H = A1;
122 R0 = A0, R1.H = A1;
124 R0 = R1 +|+ R2, R0 = R1 -|- R2;
125 R0 = R4 +|+ R5, R1 = R6 -|- R7;
126 R1 = R3 +|- R7, R1 = R3 -|+ R7; define
[all …]
Dvector.d8 0: 0c c4 0d 08 R4.H = R4.L = SIGN \(R1.H\) \* R5.H \+ SIGN \(R1.L\) \* R5.L;
24 28: 00 c4 0b a4 R2 = R1 -\|\+ R3 \(S\);
26 30: 00 c4 0a 5a R5 = R1 \+\|- R2 \(CO\);
30 40: 01 c4 1e c2 R0 = R3 \+\|\+ R6, R1 = R3 -\|- R6 \(ASL\);
31 44: 21 c4 ca 2d R7 = R1 \+\|- R2, R6 = R1 -\|\+ R2 \(S\);
32 48: 21 c4 53 0a R1 = R2 \+\|- R3, R5 = R2 -\|\+ R3;
33 4c: 04 c4 41 8d R5 = R0 \+ R1, R6 = R0 - R1 \(NS\);
34 50: 04 c4 39 a6 R0 = R7 \+ R1, R3 = R7 - R1 \(S\);
39 5c: 81 c6 8b 03 R1 = R3 >>> 0xf \(V\);
48 78: 81 c6 11 80 R0 = R1 << 0x2 \(V\);
[all …]
Dlogical2.s13 r7 = R7 & R1;
15 R1 = R7 & R7; define
17 r3 = R7 & R1;
29 R7 = R7 | R1;
32 R1 = R7 | R7; define
33 R2 = R7 | R1;
39 R7 = R7 ^ R1;
42 R1 = R7 ^ R7; define
43 R2 = R7 ^ R1;
48 R0.L = CC = BXORSHIFT(A0, R1);
[all …]
/toolchain/binutils/binutils-2.25/opcodes/
Dia64-opc-m.c104 {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY},
105 {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY},
118 {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}, EMPTY},
133 {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}, EMPTY},
135 {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV, 0, NULL},
137 {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS, 0, NULL},
138 {"alloc", M, OpX3 (1, 6), {R1, SOF, SOL, SOR}, PSEUDO|FIRST|NO_PRED|MOD_RRBS, 0, NULL},
142 {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV, 0, NULL},
143 {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}, EMPTY},
144 {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY},
[all …]
Dlm32-opc.c154 { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } },
160 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } },
166 { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } },
172 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } },
178 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (HI16), 0 } },
196 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
202 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
208 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
214 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
220 { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } },
[all …]
Dia64-opc-i.c134 {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY},
139 {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY},
140 {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY},
143 {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY},
144 {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
145 {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
146 {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
147 {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
148 {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
149 {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
[all …]
Dv850-opc.c974 #define R1 (UNUSED + 1) macro
978 #define R1_NOTR0 (R1 + 1)
1294 #define IF1 {R1, R2}
1303 #define IF6 {I16, R1, R2}
1306 #define IF6U {I16U, R1, R2}
1350 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V85…
1443 { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850…
1444 { "bins", two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850…
1445 { "bins", two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850…
1447 { "binsu",two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850…
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic4x/
Dopcodes.s408 …C3X & absf_B: & absf R1, R0 & …
409 …R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf *+AR0(1), R0 & .endif …
411 …R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi *+AR0(1), R0 & .endif …
414 …C3X & addf_B: & addf R1, R0 & …
415 …R1, R0 & addf R1, R0 & addf R1, *+AR0(1), R0 …
416 …R1, R0 &|| stf R1, *+AR1(1) & addf *+AR0(1), R0 &|| stf R1, …
419 …R1, R0 &|| sti R1, *+AR1(1) & addi *+AR0(1), R0 &|| sti R1, …
422 …R1, R0 &|| sti R1, *+AR1(1) & and *+AR0(1), R0 &|| sti R1, *…
427 …R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, *+AR0(1), R0 & .endi…
437 …C3X & cmpf_B: & cmpf R1, R0 & …
[all …]
Dopclasses.h110 name R1, R0 /* q;R */ &\
202 name R1, R0 /* q;r */ &\
237 name R1, R0 /* q;r */ &\
339 name *+AR0(1), R0 &|| name *+AR1(1), R1 /* i;L|J,K */ &\
340 name##2 *+AR0(1), R0 &|| name##1 *+AR1(1), R1 /* i;L|J,K */ &\
341 name##1 *+AR1(1), R1 &|| name##2 *+AR0(1), R0 /* J,K|i;L */ &\
345 name R0, R0 &|| name *+AR1(1), R1 /* i;L|J,K */ &\
346 name R0 &|| name *+AR1(1), R1 /* i;L|J,K */ &\
347 name##2 R0, R0 &|| name##1 *+AR1(1), R1 /* i;L|J,K */ &\
348 name##2 R0 &|| name##1 *+AR1(1), R1 /* i;L|J,K */ &\
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
Dunwind-ok.d8 [[:space:]]*R1:prologue\(rlen=8\)
16 [[:space:]]*R1:body\(rlen=25\)
55 [[:space:]]*R1:body\(rlen=0\)
56 [[:space:]]*R1:prologue\(rlen=0\)
57 [[:space:]]*R1:body\(rlen=0\)
58 [[:space:]]*R1:prologue\(rlen=0\)
59 [[:space:]]*R1:body\(rlen=0\)
60 [[:space:]]*R1:prologue\(rlen=0\)
61 [[:space:]]*R1:body\(rlen=0\)
62 [[:space:]]*R1:prologue\(rlen=0\)
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/xgate/
Dall_insns.d10 0+0000 <L0> adc R1, R2, R3
15 0+000a <L4> addh R1, #0xff
20 0+0014 <L8> andl R1, #0x04
21 0+0016 <L8\+0x2> andh R1, #0x80 Abs\* 0x00008004 <END_CODE\+0x7f1c>
35 0+002a <L15> asr R1, R2
41 0+0036 <L21> bfins R0, R1, R2
48 0+0044 <L28> bith R1, #0x20
61 0+005e <L41> sub R0, R1, R2
65 0+0066 <L45> cmpl R1, #0xff Abs\* 0x0000ffdd <END_CODE\+0xfef5>
66 0+0068 <L45\+0x2> cpch R1, #0xff
[all …]

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