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Searched refs:RA (Results 1 – 25 of 39) sorted by relevance

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/toolchain/binutils/binutils-2.25/opcodes/
Dor1k-opc.c284 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } },
290 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
296 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
302 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
308 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
314 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
320 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
326 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
332 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
338 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
[all …]
Dppc-opc.c457 #define RA NSI + 1 macro
462 #define RA0 RA + 1
2782 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2783 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2784 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2785 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2786 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2787 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2788 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2789 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
[all …]
Dor1k-opinst.c114 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
121 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
129 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
137 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
145 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
155 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
163 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
171 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
179 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
187 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
[all …]
Dalpha-opc.c206 #define RA (UNUSED + 1) macro
208 #define RB (RA + 1)
409 #define ARG_BRA { RA, BDISP }
413 #define ARG_MEM { RA, MDISP, PRB }
415 #define ARG_OPR { RA, RB, DRC1 }
416 #define ARG_OPRL { RA, LIT, DRC1 }
420 #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }
421 #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }
422 #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }
423 #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB }
[all …]
Dcr16-opc.c483 REG(RA, 0xe, CR16_R_REGTYPE),
DChangeLog-020325 (RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
987 (RA): Set to NB + 1.
1318 (RA): Update.
DChangeLog-2012657 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
Dnds32-asm.c218 #define RA(r) (r << 15) macro
DChangeLog-9899177 * alpha-opc.c (fetch, fetch_m, ecb, wh64): RA must be R31.
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/
Dpush_test.s5 # push uimm3 regr RA
7 push $1,r7,RA
8 push $2,r6,RA
9 push $3,r5,RA
10 push $4,r4,RA
11 push $5,r3,RA
12 push $6,r2,RA
13 push $7,r1,RA
14 #push $6,r12,RA
15 #push $7,r13,RA
[all …]
Dpop_test.s5 # pop uimm3 regr RA
7 pop $1,r7,RA
8 pop $2,r6,RA
9 pop $3,r5,RA
10 pop $4,r4,RA
11 pop $5,r3,RA
12 pop $6,r2,RA
13 pop $7,r1,RA
25 # pop RA
27 pop RA
Dpopret_test.s5 # popret uimm3 regr RA
7 popret $1,r7,RA
8 popret $2,r6,RA
9 popret $3,r5,RA
10 popret $4,r4,RA
11 popret $5,r3,RA
12 popret $6,r2,RA
13 popret $7,r1,RA
25 # popret RA
27 popret RA
Dpush_test.d10 0: 87 01 push \$0x1,r7,RA
11 2: 96 01 push \$0x2,r6,RA
12 4: a5 01 push \$0x3,r5,RA
13 6: b4 01 push \$0x4,r4,RA
14 8: c3 01 push \$0x5,r3,RA
15 a: d2 01 push \$0x6,r2,RA
16 c: e1 01 push \$0x7,r1,RA
25 1e: 1e 01 push RA
26 20: 1e 01 push RA
Dpopret_test.d10 0: 87 03 popret \$0x1,r7,RA
11 2: 96 03 popret \$0x2,r6,RA
12 4: a5 03 popret \$0x3,r5,RA
13 6: b4 03 popret \$0x4,r4,RA
14 8: c3 03 popret \$0x5,r3,RA
15 a: d2 03 popret \$0x6,r2,RA
16 c: e1 03 popret \$0x7,r1,RA
24 1c: 1e 03 popret RA
Dpop_test.d10 0: 87 02 pop \$0x1,r7,RA
11 2: 96 02 pop \$0x2,r6,RA
12 4: a5 02 pop \$0x3,r5,RA
13 6: b4 02 pop \$0x4,r4,RA
14 8: c3 02 pop \$0x5,r3,RA
15 a: d2 02 pop \$0x6,r2,RA
16 c: e1 02 pop \$0x7,r1,RA
24 1c: 1e 02 pop RA
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/
Dmetacore12.s79 ADDLE RA,D0Re0,A1LbP
80 ADDLE RA,D0Re0,D1.7
81 ADDPL RA,D0.7,D0Re0
82 ADDLE RA,D0.7,D1Re0
83 ADDLE RA,D0.7,A0.7
169 ADDLE RA,D1Re0,A1LbP
170 ADDLE RA,D1Re0,D0.7
171 ADDPL RA,D1.7,D1Re0
172 ADDLE RA,D1.7,D0Re0
173 ADDLE RA,D1.7,A0.7
[all …]
Dmetacore12.d87 .*: 048002dd ADDLE RA,D0Re0,A1LbP
88 .*: 04801edd ADDLE RA,D0Re0,D1\.7
89 .*: 0481c0cc ADDPL RA,D0\.7,D0Re0
90 .*: 0481d0dd ADDLE RA,D0\.7,D1Re0
91 .*: 0481fedd ADDLE RA,D0\.7,A0\.7
177 .*: 058002dd ADDLE RA,D1Re0,A1LbP
178 .*: 05801edd ADDLE RA,D1Re0,D0\.7
179 .*: 0581c0cc ADDPL RA,D1\.7,D1Re0
180 .*: 0581d0dd ADDLE RA,D1\.7,D0Re0
181 .*: 0581fedd ADDLE RA,D1\.7,A0\.7
[all …]
Dmetacore21.s64 ADDGE RA,D0Re0,A1LbP
65 ADDCS RA,D0.7,D0Re0
66 ADDGT RA,D0.7,A0.7
124 ADDVS RA,D1Re0,A0FrP
125 ADDGT RA,D1.7,RD
155 ADD RA,D0.7,#0x7f
243 ADDSVS RA,D0Re0,D1.7
244 ADDSVS RA,D0.7,D1Re0
302 ADDSGT RA,D1Re0,A1.7
303 ADDSMI RA,D1.7,D1.7
[all …]
Dmetacore21.d72 .*: 048002d7 ADDGE RA,D0Re0,A1LbP
73 .*: 0481c0c6 ADDCS RA,D0\.7,D0Re0
74 .*: 0481fedb ADDGT RA,D0\.7,A0\.7
132 .*: 058032cf ADDVS RA,D1Re0,A0FrP
133 .*: 0581e0db ADDGT RA,D1\.7,RD
163 .*: 0681dfec ADD RA,D0\.7,#0x7f
251 .*: 0c801ecf ADDSVS RA,D0Re0,D1\.7
252 .*: 0c81d0cf ADDSVS RA,D0\.7,D1Re0
310 .*: 0d800edb ADDSGT RA,D1Re0,A1\.7
311 .*: 0d81ceca ADDSMI RA,D1\.7,D1\.7
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
Dforward.s6 RA == rA label
15 dep.z RA = one, two + 3, three + 4
25 dep.z RA = one, two + 3, three + 4
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-elf/
Deh4.s38 .byte 0x10 # CIE RA Column
69 .byte 0x10 # CIE RA Column
/toolchain/binutils/binutils-2.25/include/opcode/
Dcr16.h38 era = 14, sp = 15, RA, enumerator
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-cr16.c2122 if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA))) in warn_if_needed()
2142 if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA))) in warn_if_needed()
Dtc-mips.c105 #define RA 31 macro
5524 else if (regno1 == RA && regno2 == RA) in match_entry_exit_operand()
8809 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); in macro_build_jalr()
8814 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); in macro_build_jalr()
11113 op[0] = RA; in macro()
11126 op[0] = RA; in macro()
11135 && op[0] == RA in macro()
11155 && op[0] == RA in macro()
12121 macro_build (NULL, "jr", "s", RA); in macro()
12232 if (op[0] != RA) in macro()
[all …]
/toolchain/binutils/binutils-2.25/bfd/
Delfxx-mips.c13040 #define RA 31 macro
13320 && reg != JR16_REG (opcode) && reg != RA)) in check_br16()
13339 || (MATCH (opcode, jal_x_insn_32_bd32) && reg != RA) in check_br32()
13345 && reg != OP32_SREG (opcode) && reg != RA) in check_br32()

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