| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | fr30-opc.c | 182 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
188 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
194 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
200 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
206 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
212 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
218 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
224 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
230 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
236 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
[all …]
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| D | i370-opc.c | 378 #define RI(op, r1, i2) \ macro
382 #define RI_MASK RI (0xfff, 0x0, 0x0)
787 { "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
788 { "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
789 { "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
790 { "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
791 { "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
792 { "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
793 { "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
794 { "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
[all …]
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| D | m10300-opc.c | 291 #define RI (IMM8_MEM+1) macro
295 #define SD24 (RI+1)
521 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
528 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
667 { "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
668 { "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
714 { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
715 { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
1026 { "dcpf", 0xfba60000, 0xffff00ff, 0, FMT_D7, AM33_2, {MEM2 (RI,RM0)}},
1052 { "fmov", 0xfb270000, 0xffff000d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FSN1}},
[all …]
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| /toolchain/binutils/binutils-2.25/cpu/ |
| D | mep-core.cpu | 2129 ; These instructions become the RI when the 32-bit multiply
2251 ; These instructions become the RI when the 32-bit divide instruction
2294 ; These instructions become the RI when the debug function option is
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| /toolchain/binutils/binutils-2.25/gas/doc/ |
| D | c-s390.texi | 337 @item RI format: <insn> R1,I2
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| /toolchain/binutils/binutils-2.25/gas/po/ |
| D | uk.po | 9019 msgid "RI, #imm4"
9020 msgstr "RI, #imm4"
9023 msgid "RD, (RI,#offs5)"
9024 msgstr "RD, (RI,#offs5)"
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| D | gas.pot | 9109 msgid "RI, #imm4"
9113 msgid "RD, (RI,#offs5)"
|