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Searched refs:SA (Results 1 – 13 of 13) sorted by relevance

/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dmxu.d33 [0-9a-f]+ <[^>]*> 7210c84a d16mac xr1,xr2,xr3,xr4,SA,WW
34 [0-9a-f]+ <[^>]*> 7250c84a d16mac xr1,xr2,xr3,xr4,SA,LW
35 [0-9a-f]+ <[^>]*> 7290c84a d16mac xr1,xr2,xr3,xr4,SA,HW
36 [0-9a-f]+ <[^>]*> 72d0c84a d16mac xr1,xr2,xr3,xr4,SA,XW
37 [0-9a-f]+ <[^>]*> 7210c84a d16mac xr1,xr2,xr3,xr4,SA,WW
38 [0-9a-f]+ <[^>]*> 7250c84a d16mac xr1,xr2,xr3,xr4,SA,LW
39 [0-9a-f]+ <[^>]*> 7290c84a d16mac xr1,xr2,xr3,xr4,SA,HW
40 [0-9a-f]+ <[^>]*> 72d0c84a d16mac xr1,xr2,xr3,xr4,SA,XW
65 [0-9a-f]+ <[^>]*> 7210c84b d16macf xr1,xr2,xr3,xr4,SA,WW
66 [0-9a-f]+ <[^>]*> 7250c84b d16macf xr1,xr2,xr3,xr4,SA,LW
[all …]
Dmxu.s28 \insn xr1, xr2, xr3, xr4,SA,WW
29 \insn xr1, xr2, xr3, xr4,SA,LW
30 \insn xr1, xr2, xr3, xr4,SA,HW
31 \insn xr1, xr2, xr3, xr4,SA,XW
33 \insn xr1, xr2, xr3, xr4,SA,0
34 \insn xr1, xr2, xr3, xr4,SA,1
35 \insn xr1, xr2, xr3, xr4,SA,2
36 \insn xr1, xr2, xr3, xr4,SA,3
51 \insn xr1, xr2, xr3, xr4, SA
223 q8add xr1, xr2, xr3,SA
/toolchain/binutils/binutils-2.25/gas/config/
Drl78-parse.y97 #define SA(e) if (!expr_is_saddr (e)) NOT_SADDR; macro
205 | addsub EXPR {SA($2)} ',' '#' EXPR
217 | addsub A ',' EXPR {SA($4)}
252 | addsubw AX ',' EXPR {SA($4)}
425 | oneclrb EXPR {SA($2)}
452 | CMP0 EXPR {SA($2)}
468 | incdec EXPR {SA($2)}
484 | incdecw EXPR {SA($2)}
602 | MOV regb_na ',' opt_es EXPR {SA($5)} {NOT_ES}
615 | MOV sfr ',' opt_es EXPR {SA($5)} {NOT_ES}
[all …]
/toolchain/binutils/binutils-2.25/opcodes/
Dmsp430-decode.opc88 #define SA(a) OP (1, MSP430_Operand_Indirect, MSR_None, a)
214 SA (x + ld->pc + ld->op_ptr - 2);
218 SA (x);
239 SA (0);
448 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
558 ID (MSO_call); SA (IMMU(2) | (extb << 16));
566 ID (MSO_call); SA (pc + raddr + msp430->n_bytes);
Dmsp430-decode.c89 #define SA(a) OP (1, MSP430_Operand_Indirect, MSR_None, a) macro
215 SA (x + ld->pc + ld->op_ptr - 2); in encode_as()
219 SA (x); in encode_as()
240 SA (0); in encode_as()
423 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr); in msp430_decode_opcode()
1952 ID (MSO_call); SA (IMMU(2) | (extb << 16)); in msp430_decode_opcode()
1990 ID (MSO_call); SA (pc + raddr + msp430->n_bytes); in msp430_decode_opcode()
DChangeLog-92973169 (SC_MASK): Mask out SA and LK bits.
/toolchain/binutils/binutils-2.25/ld/emultempl/
Dlnk960.em159 { bfd_mach_i960_ka_sa ,"SA" },
/toolchain/binutils/binutils-2.25/ld/
Dfdl.texi443 ``CC-BY-SA'' means the Creative Commons Attribution-Share Alike 3.0
459 under CC-BY-SA on the same site at any time before August 1, 2009,
/toolchain/binutils/binutils-2.25/bfd/doc/
Dfdl.texi443 ``CC-BY-SA'' means the Creative Commons Attribution-Share Alike 3.0
459 under CC-BY-SA on the same site at any time before August 1, 2009,
/toolchain/binutils/binutils-2.25/binutils/doc/
Dfdl.texi443 ``CC-BY-SA'' means the Creative Commons Attribution-Share Alike 3.0
459 under CC-BY-SA on the same site at any time before August 1, 2009,
/toolchain/binutils/binutils-2.25/gas/doc/
Dfdl.texi443 ``CC-BY-SA'' means the Creative Commons Attribution-Share Alike 3.0
459 under CC-BY-SA on the same site at any time before August 1, 2009,
/toolchain/binutils/binutils-2.25/gprof/
Dfdl.texi443 ``CC-BY-SA'' means the Creative Commons Attribution-Share Alike 3.0
459 under CC-BY-SA on the same site at any time before August 1, 2009,
/toolchain/binutils/binutils-2.25/bfd/
DpeXXigen.c667 #define SA(x) (((x) + sa -1 ) & (- sa)) in _bfd_XXi_swap_aouthdr_out() macro
736 + SA (FA (pei_section_data (abfd, sec)->virt_size))); in _bfd_XXi_swap_aouthdr_out()