| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | rl78-decode.opc | 118 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
215 ID(add); DR(A); SC(IMMU(1)); Fzac;
227 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
247 ID(addc); DR(A); SC(IMMU(1)); Fzac;
259 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
270 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
279 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
299 ID(and); DR(A); SC(IMMU(1)); Fz;
311 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
437 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
[all …]
|
| D | rl78-decode.c | 119 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c) macro
257 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac; in rl78_decode_opcode()
319 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
351 ID(add); DR(A); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
411 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
503 ID(mov); DM(B, IMMU(2)); SC(IMMU(1)); in rl78_decode_opcode()
518 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
550 ID(addc); DR(A); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
610 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
663 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac; in rl78_decode_opcode()
[all …]
|
| D | rx-decode.opc | 113 #define SC(i) OP (1, RX_Operand_Immediate, 0, i)
285 ID(mov); DR(rdst); SC(IMM (1)); F_____;
294 SC(IMM(im));
299 SC(IMMex(im));
304 ID(mov); DR(rdst); SC(immm); F_____;
307 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
392 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z);
395 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz);
401 ID(rtsd); SC(IMM(1) * 4);
404 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
[all …]
|
| D | msp430-decode.opc | 85 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c)
202 SC (0);
221 SC (1);
233 SC (4);
236 SC (2);
252 SC (x);
256 SC (8);
259 SC (-1);
430 PC+X *as* the address. So we use SC to use the address, not the
432 ID (MSO_jmp); SC (pc + raddr + msp430->n_bytes);
[all …]
|
| D | rx-decode.c | 114 #define SC(i) OP (1, RX_Operand_Immediate, 0, i) macro
3658 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____; in rx_decode_opcode()
3703 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb); in rx_decode_opcode()
4232 ID(add); SC(immm); DR(rdst); F_OSZC; in rx_decode_opcode()
4259 ID(mul); DR(rdst); SC(immm); F_____; in rx_decode_opcode()
4286 ID(and); SC(immm); DR(rdst); F__SZ_; in rx_decode_opcode()
4313 ID(or); SC(immm); DR(rdst); F__SZ_; in rx_decode_opcode()
4340 ID(mov); DR(rdst); SC(immm); F_____; in rx_decode_opcode()
4357 ID(rtsd); SC(IMM(1) * 4); in rx_decode_opcode()
4560 ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC; in rx_decode_opcode()
[all …]
|
| D | msp430-decode.c | 86 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c) macro
203 SC (0); in encode_as()
222 SC (1); in encode_as()
234 SC (4); in encode_as()
237 SC (2); in encode_as()
253 SC (x); in encode_as()
257 SC (8); in encode_as()
260 SC (-1); in encode_as()
549 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr); in msp430_decode_opcode()
573 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr); in msp430_decode_opcode()
[all …]
|
| D | ia64-waw.tbl | 47 CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 5.8.3.4, "End of External Interrupt Registe…
63 CR[IVR]; IC:none; IC:none; SC
64 CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC
83 InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC
90 MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC
|
| D | ia64-raw.tbl | 48 CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 5.8.3.4, "End of External Interrupt Register (EOI - …
70 CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 5.8.3.2, "External Interrupt Vector Register (IVR …
71 CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 5.8.3.1, "Local ID (LID - CR64)" on page …
76 CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l+17, ssm+17; SC Section 5.8.3.3, "Task Priority Register …
121 PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC Section 7.2.1, "Generic Performance Counter Re…
|
| D | ppc-opc.c | 2291 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) macro
3809 {"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
3810 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
3811 {"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
3812 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
3813 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}},
|