| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | rl78-decode.opc | 122 #define SM(r,a) OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a)
200 ID(add); DR(A); SM(None, IMMU(2)); Fzac;
203 ID(add); DR(A); SM(HL, 0); Fzac;
209 ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
221 ID(add); DR(A); SM(None, SADDR); Fzac;
232 ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
235 ID(addc); DR(A); SM(HL, 0); Fzac;
244 ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
256 ID(addc); DR(A); SM(None, SADDR); Fzac;
264 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
[all …]
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| D | rl78-decode.c | 123 #define SM(r,a) OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a) macro
242 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac; in rl78_decode_opcode()
272 ID(add); W(); DR(AX); SM(None, SADDR); Fzac; in rl78_decode_opcode()
304 ID(mov); DR(A); SM(B, IMMU(2)); in rl78_decode_opcode()
336 ID(add); DR(A); SM(None, SADDR); Fzac; in rl78_decode_opcode()
366 ID(add); DR(A); SM(HL, 0); Fzac; in rl78_decode_opcode()
381 ID(add); DR(A); SM(HL, IMMU(1)); Fzac; in rl78_decode_opcode()
396 ID(add); DR(A); SM(None, IMMU(2)); Fzac; in rl78_decode_opcode()
535 ID(addc); DR(A); SM(None, SADDR); Fzac; in rl78_decode_opcode()
565 ID(addc); DR(A); SM(HL, 0); Fzac; in rl78_decode_opcode()
[all …]
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| D | micromips-opc.c | 204 #define SM INSN_STORE_MEMORY macro
316 {"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 },
348 {"aset", "\\,~(b)", 0x20003000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 },
953 {"sb", "mq,mL(ml)", 0x8800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 },
954 {"sb", "t,o(b)", 0x18000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
956 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 },
958 {"scd", "t,~(b)", 0x6000f000, 0xfc00f000, MOD_1|RD_3|SM, 0, I3, 0, 0 },
962 {"sd", "t,o(b)", 0xd8000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 },
967 {"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 },
968 {"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 },
[all …]
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| D | mips-opc.c | 281 #define SM INSN_STORE_MEMORY macro
515 {"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
516 {"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
517 {"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
518 {"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
519 {"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
520 {"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
521 {"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
522 {"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
527 {"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
[all …]
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| D | msp430-decode.opc | 87 #define SM(r, a) OP (1, MSP430_Operand_Indirect, r, a)
225 SM (reg, x);
241 SM (reg, 0);
428 /* This is a pc-relative jump, but we don't use SM because that
438 ID (MSO_mov); SM (srcr, 0); DR (dstr);
453 ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr);
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| D | msp430-decode.c | 88 #define SM(r, a) OP (1, MSP430_Operand_Indirect, r, a) macro
226 SM (reg, x); in encode_as()
242 SM (reg, 0); in encode_as()
375 ID (MSO_mov); SM (srcr, 0); DR (dstr); in msp430_decode_opcode()
447 ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr); in msp430_decode_opcode()
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| /toolchain/binutils/binutils-2.25/cpu/ |
| D | or1kcommon.cpu | 240 (SYS SR SM 0 0 "supervisor mode bit")
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| /toolchain/binutils/binutils-2.25/ |
| D | config.guess | 1168 SM[BE]S:UNIX_SV:*:*)
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| /toolchain/binutils/binutils-2.25/ld/po/ |
| D | tr.po | 1254 msgstr "DOSYAİSMİ"
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| /toolchain/binutils/binutils-2.25/gas/ |
| D | ChangeLog-9899 | 1406 SM. Add member EMPTY_SEQUENCE to keep track if a code sequence
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