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Searched refs:V8 (Results 1 – 12 of 12) sorted by relevance

/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/
Dticc-imm-reg.s1 ! Make ticc aliases operate as per V8 SPARC Architecture Manual
Dsplet.s47 stbar ! is a valid V8 syntax, at least a synthetic
55 flush %l1 ! is the official V8 syntax
Dv8-movwr-imm.s1 ! Make 'mov' and 'wr' aliases operate as per V8 SPARC Architecture Manual
Dv8-movwr-imm.d3 #name: V8 mov/wr aliases
/toolchain/binutils/binutils-2.25/gold/
Darm.cc10820 T(V8), // PRE_V4. in tag_cpu_arch_combine()
10821 T(V8), // V4. in tag_cpu_arch_combine()
10822 T(V8), // V4T. in tag_cpu_arch_combine()
10823 T(V8), // V5T. in tag_cpu_arch_combine()
10824 T(V8), // V5TE. in tag_cpu_arch_combine()
10825 T(V8), // V5TEJ. in tag_cpu_arch_combine()
10826 T(V8), // V6. in tag_cpu_arch_combine()
10827 T(V8), // V6KZ. in tag_cpu_arch_combine()
10828 T(V8), // V6T2. in tag_cpu_arch_combine()
10829 T(V8), // V6K. in tag_cpu_arch_combine()
[all …]
DChangeLog409 * arm.cc: Add V8 arch combine table.
/toolchain/binutils/binutils-2.25/opcodes/
Dv850-opc.c1166 #define V8 (D8_6U + 1) macro
1170 #define I9 (V8 + 1)
1911 { "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3_UP },
DChangeLog-2011169 with the V8 SPARC Architecture Manual.
/toolchain/binutils/binutils-2.25/bfd/
Delf32-arm.c11551 T(V8), /* PRE_V4. */ in tag_cpu_arch_combine()
11552 T(V8), /* V4. */ in tag_cpu_arch_combine()
11553 T(V8), /* V4T. */ in tag_cpu_arch_combine()
11554 T(V8), /* V5T. */ in tag_cpu_arch_combine()
11555 T(V8), /* V5TE. */ in tag_cpu_arch_combine()
11556 T(V8), /* V5TEJ. */ in tag_cpu_arch_combine()
11557 T(V8), /* V6. */ in tag_cpu_arch_combine()
11558 T(V8), /* V6KZ. */ in tag_cpu_arch_combine()
11559 T(V8), /* V6T2. */ in tag_cpu_arch_combine()
11560 T(V8), /* V6K. */ in tag_cpu_arch_combine()
[all …]
DChangeLog-2006235 * peXXigen.c: Updates for PE/COFF V8.0, and clarification
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-sparc.texi332 The V8 co-processor queue register is referred to as @samp{%cq}.
389 The V8 window invalid mask register is referred to as @samp{%wim}.
392 The V8 processor state register is referred to as @samp{%psr}.
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-arm.c17909 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),