Searched refs:architectures (Results 1 – 25 of 114) sorted by relevance
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| /toolchain/binutils/binutils-2.25/bfd/ |
| D | cpu-arm.c | 354 architectures[] = variable
401 for (i = ARRAY_SIZE (architectures); i--;) in bfd_arm_get_mach_from_notes()
402 if (strcmp (arch_string, architectures[i].string) == 0) in bfd_arm_get_mach_from_notes()
405 return architectures[i].mach; in bfd_arm_get_mach_from_notes()
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| /toolchain/binutils/binutils-2.25/gas/doc/ |
| D | c-metag.texi | 28 @cindex architectures, Meta
29 @cindex Meta architectures
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| D | c-score.texi | 26 @cindex architectures, SCORE
27 @cindex SCORE architectures
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| D | c-ppc.texi | 27 @cindex architectures, PowerPC
28 @cindex PowerPC architectures
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| D | all.texi | 9 @c Discuss all architectures?
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| D | c-i960.texi | 46 960 (even if this means mixing architectures!). In principle,
59 architectures.) If @var{BR} represents a conditional branch instruction,
231 The 960 architectures provide combined Compare-and-Branch instructions
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| D | c-microblaze.texi | 14 @cindex MicroBlaze architectures
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| D | c-sparc.texi | 28 @cindex architectures, SPARC
29 @cindex SPARC architectures
38 successively higher architectures as it encounters instructions that
79 architectures explicitly. If you select an architecture explicitly,
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| D | c-arm.texi | 147 Some extensions may be restricted to particular architectures; this is
160 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
164 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
166 @code{sec} (Security Extensions for v6K and v7-A architectures),
267 architectures the default is to assemble for FPA instructions.
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| D | c-nds32.texi | 19 architectures supports NDS32 ISA version 3. For detail about NDS32
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| D | c-sh.texi | 203 conventional architectures at the same frequency.
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| D | c-m32r.texi | 261 from now on. An instructions from later M32R architectures are
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| D | arm-it-bad-3.d | 1 #name: Test automatic IT generation in Thumb-1 architectures.
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| D | arm-it.s | 1 # Check that IT is accepted in ARM mode on older architectures
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| D | attr-merge-arch-2.d | 5 #error: Conflicting CPU architectures 13/0
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-scripts/ |
| D | phdrs.t | 10 /* This test will fail on architectures where the startaddress below
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| D | phdrs3a.t | 9 /* This test will fail on architectures where the startaddress below
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| D | phdrs3.t | 10 /* This test will fail on architectures where the startaddress below
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| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | cgen-ibld.in | 143 /* For architectures with insns smaller than the base-insn-bitsize,
301 /* For architectures with insns smaller than the base-insn-bitsize,
447 /* For architectures with insns smaller than the insn-base-bitsize,
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| /toolchain/binutils/binutils-2.25/cpu/ |
| D | or1k.cpu | 22 ; The OpenRISC family is a set of RISC microprocessor architectures with an
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| /toolchain/binutils/binutils-2.25/binutils/ |
| D | NEWS | 41 * Add support for the Tilera TILEPro and TILE-Gx architectures.
311 * Add support for ARM v5t and v5te architectures and Intel's XScale ARM
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| D | README | 145 Binutils-2.13 supports many different architectures, but there
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| /toolchain/binutils/binutils-2.25/gas/ |
| D | NEWS | 50 * Add support for the Tilera TILEPro and TILE-Gx architectures.
226 * On ARM architectures, added a new gas directive ".unreq" that undoes
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| /toolchain/binutils/binutils-2.25/ld/ |
| D | ChangeLog-2011 | 778 * Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
789 Add avrxmega6, avrxmega7 to list of architectures for no stubs.
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| /toolchain/binutils/binutils-2.25/gold/ |
| D | configure.ac | 342 dnl Some architectures do not support taking pointers of functions
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