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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/alpha/
Delf-reloc-5.d9 0: 05 00 e0 c3 br 18 <nopv>
10 4: 04 00 e0 c3 br 18 <nopv>
11 8: 04 00 e0 c3 br 1c <stdgp>
12 c: 05 00 e0 c3 br 24 <stdgp\+0x8>
13 10: 00 00 e0 c3 br 14 <_start\+0x14>
15 14: 00 00 e0 c3 br 18 <nopv>
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/
Dpower4.d55 .*: (e0 c3 00 00|00 00 c3 e0) lq r6,0\(r3\)
57 .*: (e0 c3 00 00|00 00 c3 e0) lq r6,0\(r3\)
59 .*: (e0 c3 00 00|00 00 c3 e0) lq r6,0\(r3\)
61 .*: (e0 c3 00 .0|.0 00 c3 e0) lq r6,.*\(r3\)
63 .*: (e0 c3 00 .0|.0 00 c3 e0) lq r6,.*\(r3\)
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/
Dmcf-movsr.d10 0: 46c3 movew %d3,%sr
12 6: 40c3 movew %sr,%d3
13 8: 44c3 movew %d3,%ccr
15 e: 42c3 movew %ccr,%d3
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Darith_mode.d14 14: c3 c0 00 38 R0.L = A0 \(TFU\);
26 44: 04 c3 0a 40 R0.H = R1.L \* R2.H \(IS\);
27 48: 84 c3 0a 40 R0.H = R1.L \* R2.H \(IU\);
31 58: 24 c3 0a 40 R0.H = R1.L \* R2.H \(ISS2\);
32 5c: 64 c3 0a 40 R0.H = R1.L \* R2.H \(IH\);
35 68: 08 c3 0a 22 R0 = R1.L \* R2.H \(IS\);
37 70: 28 c3 0a 22 R0 = R1.L \* R2.H \(ISS2\);
47 98: c3 c0 0a 22 R0.L = \(A0 = R1.L \* R2.H\) \(TFU\);
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dmpx-add-bnd-prefix.d16 [ ]*[a-f0-9]+: f2 c3 bnd ret
19 [ ]*[a-f0-9]+: f2 c3 bnd ret
20 [ ]*[a-f0-9]+: f2 c3 bnd ret
22 [ ]*[a-f0-9]+: 01 c3 add %eax,%ebx
Dx86-64-mpx-add-bnd-prefix.d16 [ ]*[a-f0-9]+: f2 c3 bnd retq
19 [ ]*[a-f0-9]+: f2 c3 bnd retq
20 [ ]*[a-f0-9]+: f2 c3 bnd retq
22 [ ]*[a-f0-9]+: 48 01 c3 add %rax,%rbx
Dvmx.d11 6: 0f 01 c3 [ ]*vmresume
17 1a: 0f 78 c3 [ ]*vmread %eax,%ebx
18 1d: 0f 78 c3 [ ]*vmread %eax,%ebx
Dx86-64-vmx.d11 6: 0f 01 c3 [ ]*vmresume
17 1a: 0f 78 c3 [ ]*vmread %rax,%rbx
18 1d: 0f 78 c3 [ ]*vmread %rax,%rbx
Dx86-64-fsgs.d10 [ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx
11 [ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase %rbx
26 [ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx
27 [ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase %rbx
Dx86-64-fsgs-intel.d11 [ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx
12 [ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase rbx
27 [ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx
28 [ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase rbx
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/
Dstorw_test.d119 174: 3c c3 34 00 storw \$0x3:s,0x34:m\(r12\)
120 178: 3d c3 ab 00 storw \$0x3:s,0xab:m\(r13\)
129 194: 3c c3 ff 0f storw \$0x3:s,0xfff:m\(r12\)
130 198: 3d c3 ff 0f storw \$0x3:s,0xfff:m\(r13\)
131 19c: 3d c3 ff ff storw \$0x3:s,0xffff:m\(r13\)
132 1a0: 3c c3 43 23 storw \$0x3:s,0x2343:m\(r12\)
146 1ca: 51 c3 01 00 storw \$0x5:s,0x1:m\(r2,r1\)
147 1ce: 41 c3 34 12 storw \$0x4:s,0x1234:m\(r2,r1\)
148 1d2: 31 c3 34 12 storw \$0x3:s,0x1234:m\(r2,r1\)
151 1dc: 31 c3 23 01 storw \$0x3:s,0x123:m\(r2,r1\)
/toolchain/binutils/binutils-2.25/gold/testsuite/
Ddwp_test_main.cc49 assert(c3.testcase1()); in main()
50 assert(c3.testcase2()); in main()
51 assert(c3.testcase3()); in main()
Dcommon_test_1_v2.c39 int c3[30]; variable
59 assert (c4 != c3); in main()
60 assert (c3 != c2); in main()
Dcommon_test_1.c39 int c3[30]; variable
57 assert (c4 > c3); in main()
58 assert (c3 > c2); in main()
Dcommon_test_1_v1.c42 int c3[30]; variable
61 assert (c4 < c3); in main()
62 assert (c3 < c2); in main()
Dplugin_common_test_2.c31 int c3; variable
42 c3 = 30; in foo()
Dplugin_common_test_1.c31 extern int c3;
44 assert (c3 == 30); in main()
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-xstormy16/
Dpcrel.d16 801e: 24 c3 00 00 bc Rx,#0x0,0x8046
17 8022: 1c c3 00 00 bc Rx,#0x0,0x8042
18 8026: 1a c3 00 00 bc Rx,#0x0,0x8044
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/
Dx86-64-vmx.d12 6: 0f 01 c3 [ ]*vmresume
18 1a: 0f 78 c3 [ ]*vmread %rax,%rbx
19 1d: 0f 78 c3 [ ]*vmread %rax,%rbx
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/
Dcbcond.d18 20: 16 c3 48 10 cwbl %o5, %l0, 0x120
19 24: 16 c3 67 e6 cwbl %o5, 6, 0x120
54 b0: 3a c2 c3 8c cwbcc %o3, %o4, 0x120
58 c0: 3c c3 43 10 cwbpos %o5, %l0, 0x120
59 c4: 3c c3 62 f9 cwbpos %o5, 0x19, 0x120
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-i386/
Dvxworks1-lib.dd35 80c25: c3 ret
38 80c26: c3 ret
41 80c27: c3 ret
/toolchain/binutils/binutils-2.25/cpu/
Dmep-ivc2.cpu46 (define-pmacro ivc2-c3-isa () (ISA ext_cop1_32))
116 (comment "slots for which this opcode is valid - c3, p0s, p0, p1")
277 (name f-ivc2-ccrn-c3)
283 (set (ifield f-ivc2-ccrn-c3hi) (and (srl (ifield f-ivc2-ccrn-c3) 4) #x3))
284 (set (ifield f-ivc2-ccrn-c3lo) (and (ifield f-ivc2-ccrn-c3) #xf))))
285 (extract (set (ifield f-ivc2-ccrn-c3)
321 (dnop ivc2c3ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn-c3)
331 (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmov1"))
342 (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmov2"))
353 (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc1"))
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
Dopc-a.d268 560: 00 10 0c 08 c3 34 \[MII\] cmp4\.eq\.or p2,p3=r3,r4
271 570: 00 10 0c 08 c3 39 \[MII\] cmp4\.eq\.or\.andcm p2,p3=3,r4
274 580: 00 10 0e 08 c3 30 \[MII\] cmp4\.ne\.and p2,p3=r3,r4
280 5a0: 00 10 0e 08 c3 34 \[MII\] cmp4\.ne\.or p2,p3=r3,r4
283 5b0: 00 10 0e 08 c3 39 \[MII\] cmp4\.ne\.or\.andcm p2,p3=3,r4
286 5c0: 00 10 0c 08 c3 30 \[MII\] cmp4\.eq\.and p2,p3=r3,r4
291 5dc: 40 00 0c c3 cmp4\.eq\.and p2,p3=r4,r0
292 5e0: 00 10 00 08 c3 34 \[MII\] cmp4\.eq\.or p2,p3=r0,r4
295 5f0: 00 10 10 00 c3 38 \[MII\] cmp4\.eq\.or\.andcm p2,p3=r4,r0
298 600: 00 10 02 08 c3 30 \[MII\] cmp4\.ne\.and p2,p3=r0,r4
[all …]
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-cris/
Dcomref1.s5 .comm c3,4,1
8 move.d c3:PLT,$r10
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-powerpc/
Daix-weak-2a.s5 .globl c3 symbol
6 c3 = 0xcccc3333 define

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