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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dshift2.d56 60: 80 c6 00 00 R0.L = R0.L >>> 0x0;
57 64: 80 c6 88 01 R0.L = R0.L >>> 0xf;
58 68: 80 c6 00 10 R0.L = R0.H >>> 0x0;
59 6c: 80 c6 88 11 R0.L = R0.H >>> 0xf;
60 70: 80 c6 00 20 R0.H = R0.L >>> 0x0;
61 74: 80 c6 88 21 R0.H = R0.L >>> 0xf;
62 78: 80 c6 00 30 R0.H = R0.H >>> 0x0;
63 7c: 80 c6 88 31 R0.H = R0.H >>> 0xf;
64 80: 80 c6 01 00 R0.L = R1.L >>> 0x0;
65 84: 80 c6 89 01 R0.L = R1.L >>> 0xf;
[all …]
Dshift.d18 c: 83 c6 08 41 A0 = A0 >> 0x1f;
19 10: 83 c6 f8 00 A0 = A0 << 0x1f;
20 14: 83 c6 00 50 A1 = A1 >> 0x0;
21 18: 83 c6 00 10 A1 = A1 << 0x0;
22 1c: 82 c6 fd 4e R7 = R5 << 0x1f \(S\);
23 20: 82 c6 52 07 R3 = R2 >>> 0x16;
24 24: 80 c6 7a 52 R1.L = R2.H << 0xf \(S\);
25 28: 80 c6 f2 2b R5.H = R2.L >>> 0x2;
30 34: 00 c6 14 16 R3.L = ASHIFT R4.H BY R2.L;
31 38: 00 c6 07 6e R7.H = ASHIFT R7.L BY R0.L \(S\);
[all …]
Dbit2.d38 3c: 0a c6 08 8e R7 = DEPOSIT \(R0, R1\);
39 40: 0a c6 0f 8e R7 = DEPOSIT \(R7, R1\);
40 44: 0a c6 3f 8e R7 = DEPOSIT \(R7, R7\);
41 48: 0a c6 08 82 R1 = DEPOSIT \(R0, R1\);
42 4c: 0a c6 0f 84 R2 = DEPOSIT \(R7, R1\);
43 50: 0a c6 3f 86 R3 = DEPOSIT \(R7, R7\);
44 54: 0a c6 08 ce R7 = DEPOSIT \(R0, R1\) \(X\);
45 58: 0a c6 0f ce R7 = DEPOSIT \(R7, R1\) \(X\);
46 5c: 0a c6 3f ce R7 = DEPOSIT \(R7, R7\) \(X\);
47 60: 0a c6 08 c2 R1 = DEPOSIT \(R0, R1\) \(X\);
[all …]
Dbit.d24 12: 0a c6 13 8a R5 = DEPOSIT \(R3, R2\);
25 16: 0a c6 37 c0 R0 = DEPOSIT \(R7, R6\) \(X\);
28 1a: 0a c6 0a 08 R4 = EXTRACT \(R2, R1.L\) \(Z\);
29 1e: 0a c6 10 04 R2 = EXTRACT \(R0, R2.L\) \(Z\);
30 22: 0a c6 23 4e R7 = EXTRACT \(R3, R4.L\) \(X\);
31 26: 0a c6 0e 4a R5 = EXTRACT \(R6, R1.L\) \(X\);
34 2a: 08 c6 08 00 BITMUX \(R1, R0, A0\) \(ASR\);
35 2e: 08 c6 13 00 BITMUX \(R2, R3, A0\) \(ASR\);
36 32: 08 c6 25 40 BITMUX \(R4, R5, A0\) \(ASL\);
37 36: 08 c6 3e 40 BITMUX \(R7, R6, A0\) \(ASL\);
[all …]
Dlogical2.d31 2c: 0b c6 00 00 R0.L = CC = BXORSHIFT \(A0, R0\);
32 30: 0b c6 08 00 R0.L = CC = BXORSHIFT \(A0, R1\);
33 34: 0b c6 00 06 R3.L = CC = BXORSHIFT \(A0, R0\);
34 38: 0b c6 08 06 R3.L = CC = BXORSHIFT \(A0, R1\);
35 3c: 0b c6 00 40 R0.L = CC = BXOR \(A0, R0\);
36 40: 0b c6 08 40 R0.L = CC = BXOR \(A0, R1\);
37 44: 0b c6 00 46 R3.L = CC = BXOR \(A0, R0\);
38 48: 0b c6 08 46 R3.L = CC = BXOR \(A0, R1\);
39 4c: 0c c6 00 40 R0.L = CC = BXOR \(A0, A1, CC\);
40 50: 0c c6 00 40 R0.L = CC = BXOR \(A0, A1, CC\);
[all …]
Dvideo2.d8 [ 0-9a-f]+: 0d c6 00 00 R0 = ALIGN8 \(R0, R0\);
9 [ 0-9a-f]+: 0d c6 08 00 R0 = ALIGN8 \(R0, R1\);
10 [ 0-9a-f]+: 0d c6 01 00 R0 = ALIGN8 \(R1, R0\);
11 [ 0-9a-f]+: 0d c6 09 00 R0 = ALIGN8 \(R1, R1\);
12 [ 0-9a-f]+: 0d c6 11 00 R0 = ALIGN8 \(R1, R2\);
13 [ 0-9a-f]+: 0d c6 2c 06 R3 = ALIGN8 \(R4, R5\);
14 [ 0-9a-f]+: 0d c6 07 0c R6 = ALIGN8 \(R7, R0\);
15 [ 0-9a-f]+: 0d c6 1a 02 R1 = ALIGN8 \(R2, R3\);
16 [ 0-9a-f]+: 0d c6 35 08 R4 = ALIGN8 \(R5, R6\);
17 [ 0-9a-f]+: 0d c6 08 0e R7 = ALIGN8 \(R0, R1\);
[all …]
Dvector2.d16 20: 09 c6 13 8a R5 = VIT_MAX \(R3, R2\) \(ASL\);
17 24: 09 c6 01 ce R7 = VIT_MAX \(R1, R0\) \(ASR\);
18 28: 09 c6 11 80 R0 = VIT_MAX \(R1, R2\) \(ASL\);
19 2c: 09 c6 2c c6 R3 = VIT_MAX \(R4, R5\) \(ASR\);
20 30: 09 c6 07 8c R6 = VIT_MAX \(R7, R0\) \(ASL\);
21 34: 09 c6 1a c2 R1 = VIT_MAX \(R2, R3\) \(ASR\);
22 38: 09 c6 35 88 R4 = VIT_MAX \(R5, R6\) \(ASL\);
23 3c: 09 c6 08 ce R7 = VIT_MAX \(R0, R1\) \(ASR\);
24 40: 09 c6 23 84 R2 = VIT_MAX \(R3, R4\) \(ASL\);
25 44: 09 c6 3e ca R5 = VIT_MAX \(R6, R7\) \(ASR\);
[all …]
Dlogical.d29 1a: 0b c6 00 4e R7.L = CC = BXOR \(A0, R0\);
30 1e: 0b c6 08 4e R7.L = CC = BXOR \(A0, R1\);
31 22: 0c c6 00 4a R5.L = CC = BXOR \(A0, A1, CC\);
32 26: 0c c6 00 48 R4.L = CC = BXOR \(A0, A1, CC\);
35 2a: 0b c6 38 06 R3.L = CC = BXORSHIFT \(A0, R7\);
36 2e: 0b c6 10 04 R2.L = CC = BXORSHIFT \(A0, R2\);
37 32: 0c c6 00 00 A0 = BXORSHIFT \(A0, A1, CC\);
38 36: 0c c6 00 00 A0 = BXORSHIFT \(A0, A1, CC\);
Dvector.d11 4: 09 c6 15 8e R7 = VIT_MAX \(R5, R2\) \(ASL\);
12 8: 09 c6 30 c0 R0 = VIT_MAX \(R0, R6\) \(ASR\);
13 c: 09 c6 03 0a R5.L = VIT_MAX \(R3\) \(ASL\);
14 10: 09 c6 02 44 R2.L = VIT_MAX \(R2\) \(ASR\);
39 5c: 81 c6 8b 03 R1 = R3 >>> 0xf \(V\);
40 60: 81 c6 e0 09 R4 = R0 >>> 0x4 \(V\);
41 64: 81 c6 00 4a R5 = R0 << 0x0 \(V, S\);
42 68: 81 c6 62 44 R2 = R2 << 0xc \(V, S\);
43 6c: 01 c6 15 0e R7 = ASHIFT R5 BY R2.L \(V\);
44 70: 01 c6 02 40 R0 = ASHIFT R2 BY R0.L \(V, S\);
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dx86-64-avx-swap-intel.d12 [ ]*[a-f0-9]+: c5 7d 29 c6 vmovapd ymm6,ymm8
13 [ ]*[a-f0-9]+: c5 7c 29 c6 vmovaps ymm6,ymm8
14 [ ]*[a-f0-9]+: c5 7d 7f c6 vmovdqa ymm6,ymm8
15 [ ]*[a-f0-9]+: c5 7e 7f c6 vmovdqu ymm6,ymm8
16 [ ]*[a-f0-9]+: c5 7d 11 c6 vmovupd ymm6,ymm8
17 [ ]*[a-f0-9]+: c5 7c 11 c6 vmovups ymm6,ymm8
18 [ ]*[a-f0-9]+: c5 79 29 c6 vmovapd xmm6,xmm8
19 [ ]*[a-f0-9]+: c5 78 29 c6 vmovaps xmm6,xmm8
20 [ ]*[a-f0-9]+: c5 79 7f c6 vmovdqa xmm6,xmm8
21 [ ]*[a-f0-9]+: c5 7a 7f c6 vmovdqu xmm6,xmm8
[all …]
Dx86-64-avx-swap.d11 [ ]*[a-f0-9]+: c5 7d 29 c6 vmovapd %ymm8,%ymm6
12 [ ]*[a-f0-9]+: c5 7c 29 c6 vmovaps %ymm8,%ymm6
13 [ ]*[a-f0-9]+: c5 7d 7f c6 vmovdqa %ymm8,%ymm6
14 [ ]*[a-f0-9]+: c5 7e 7f c6 vmovdqu %ymm8,%ymm6
15 [ ]*[a-f0-9]+: c5 7d 11 c6 vmovupd %ymm8,%ymm6
16 [ ]*[a-f0-9]+: c5 7c 11 c6 vmovups %ymm8,%ymm6
17 [ ]*[a-f0-9]+: c5 79 29 c6 vmovapd %xmm8,%xmm6
18 [ ]*[a-f0-9]+: c5 78 29 c6 vmovaps %xmm8,%xmm6
19 [ ]*[a-f0-9]+: c5 79 7f c6 vmovdqa %xmm8,%xmm6
20 [ ]*[a-f0-9]+: c5 7a 7f c6 vmovdqu %xmm8,%xmm6
[all …]
Dx86-64-avx512pf.d11 [ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
12 [ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
13 [ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
14 [ ]*[a-f0-9]+: 62 b2 fd 41 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
15 [ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 7b 00 00 00 vgatherpf0dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
16 [ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 7b 00 00 00 vgatherpf0dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
17 [ ]*[a-f0-9]+: 62 92 7d 41 c6 4c 39 40 vgatherpf0dps 0x100\(%r9,%zmm31,1\)\{%k1\}
18 [ ]*[a-f0-9]+: 62 b2 7d 41 c6 8c b9 00 04 00 00 vgatherpf0dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
27 [ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
28 [ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
[all …]
Davx512pf.d11 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
12 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
13 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
14 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
15 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
16 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
17 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 4c 38 40 vgatherpf0dps 0x100\(%eax,%zmm7,1\)\{%k1\}
18 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c b9 00 04 00 00 vgatherpf0dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
27 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
28 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
[all …]
Dx86-64-avx512pf-intel.d12 [ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]…
13 [ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]…
14 [ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
15 [ ]*[a-f0-9]+: 62 b2 fd 41 c6 8c b9 00 04 00 00 vgatherpf0dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\…
16 [ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]…
17 [ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]…
18 [ ]*[a-f0-9]+: 62 92 7d 41 c6 4c 39 40 vgatherpf0dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
19 [ ]*[a-f0-9]+: 62 b2 7d 41 c6 8c b9 00 04 00 00 vgatherpf0dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\…
28 [ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]…
29 [ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]…
[all …]
Davx512pf-intel.d12 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\…
13 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\…
14 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
15 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]…
16 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\…
17 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\…
18 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 4c 38 40 vgatherpf0dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
19 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c b9 00 04 00 00 vgatherpf0dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]…
28 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\…
29 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\…
[all …]
Drelax-2.d10 38: 0f 85 88 00 00 00 jne (0x)?c6( .*)?
12 48: 75 7c jne (0x)?c6( .*)?
14 c6: 90 nop
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/
Dx86-64-avx-swap.d12 [ ]*[a-f0-9]+: c5 7d 29 c6 vmovapd %ymm8,%ymm6
13 [ ]*[a-f0-9]+: c5 7c 29 c6 vmovaps %ymm8,%ymm6
14 [ ]*[a-f0-9]+: c5 7d 7f c6 vmovdqa %ymm8,%ymm6
15 [ ]*[a-f0-9]+: c5 7e 7f c6 vmovdqu %ymm8,%ymm6
16 [ ]*[a-f0-9]+: c5 7d 11 c6 vmovupd %ymm8,%ymm6
17 [ ]*[a-f0-9]+: c5 7c 11 c6 vmovups %ymm8,%ymm6
18 [ ]*[a-f0-9]+: c5 79 29 c6 vmovapd %xmm8,%xmm6
19 [ ]*[a-f0-9]+: c5 78 29 c6 vmovaps %xmm8,%xmm6
20 [ ]*[a-f0-9]+: c5 79 7f c6 vmovdqa %xmm8,%xmm6
21 [ ]*[a-f0-9]+: c5 7a 7f c6 vmovdqu %xmm8,%xmm6
[all …]
Dx86-64-avx-swap-intel.d12 [ ]*[a-f0-9]+: c5 7d 29 c6 vmovapd ymm6,ymm8
13 [ ]*[a-f0-9]+: c5 7c 29 c6 vmovaps ymm6,ymm8
14 [ ]*[a-f0-9]+: c5 7d 7f c6 vmovdqa ymm6,ymm8
15 [ ]*[a-f0-9]+: c5 7e 7f c6 vmovdqu ymm6,ymm8
16 [ ]*[a-f0-9]+: c5 7d 11 c6 vmovupd ymm6,ymm8
17 [ ]*[a-f0-9]+: c5 7c 11 c6 vmovups ymm6,ymm8
18 [ ]*[a-f0-9]+: c5 79 29 c6 vmovapd xmm6,xmm8
19 [ ]*[a-f0-9]+: c5 78 29 c6 vmovaps xmm6,xmm8
20 [ ]*[a-f0-9]+: c5 79 7f c6 vmovdqa xmm6,xmm8
21 [ ]*[a-f0-9]+: c5 7a 7f c6 vmovdqu xmm6,xmm8
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/
Dstorw_test.d69 c6: cc ed
72 cc: f0 c6 04 12 storw r15,\[r12\]0x234:m\(r1,r0\)
90 10a: 30 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
91 10e: 31 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
92 112: 36 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
93 116: 32 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
94 11a: 37 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
95 11e: 33 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
96 122: 34 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
97 126: 35 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/
Daltivec.d63 d4: (11 c6 13 ca|ca 13 c6 11) vctsxs v14,v2,6
67 e4: (12 5c 03 c6|c6 03 5c 12) vcmpbfp v18,v28,v0
68 e8: (12 7a 1f c6|c6 1f 7a 12) vcmpbfp\. v19,v26,v3
69 ec: (12 02 58 c6|c6 58 02 12) vcmpeqfp v16,v2,v11
70 f0: (12 ed 6c c6|c6 6c ed 12) vcmpeqfp\. v23,v13,v13
77 10c: (12 f1 81 c6|c6 81 f1 12) vcmpgefp v23,v17,v16
78 110: (12 7d 8d c6|c6 8d 7d 12) vcmpgefp\. v19,v29,v17
79 114: (12 1c 6a c6|c6 6a 1c 12) vcmpgtfp v16,v28,v13
80 118: (11 d8 3e c6|c6 3e d8 11) vcmpgtfp\. v14,v24,v7
De500mc.d25 3c: (7c 18 cb c6|c6 cb 18 7c) dsn r24,r25
40 78: (7d f0 8c c6|c6 8c f0 7d) lddx r15,r16,r17
45 8c: (7e b6 bd c6|c6 bd b6 7e) stddx r21,r22,r23
/toolchain/binutils/binutils-2.25/gold/testsuite/
Dcommon_test_1_v2.c36 int c6[60]; variable
62 assert (c1 != c6); in main()
63 assert (c6 != c7); in main()
Dcommon_test_1.c36 int c6[60]; variable
60 assert (c1 > c6); in main()
61 assert (c6 > c7); in main()
Dcommon_test_1_v1.c39 int c6[60]; variable
64 assert (c1 < c6); in main()
65 assert (c6 < c7); in main()
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/
Dcbcond.d34 60: 1e c5 c6 18 cwbvs %l7, %i0, 0x120
38 70: 32 c6 45 9a cwbne %i1, %i2, 0x120
39 74: 32 c6 65 70 cwbne %i1, 0x10, 0x120
42 80: 34 c6 c5 1c cwbg %i3, %i4, 0x120
43 84: 34 c6 e4 f2 cwbg %i3, 0x12, 0x120

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