/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
D | r6-removed.s | 3 abs.ps $f0,$f2 4 add.ps $f0,$f2,$f2 6 alnv.ps $f0,$f2,$f2,$3 33 c.f.s $f0,$f2 34 c.un.s $f0,$f2 35 c.eq.s $f0,$f2 36 c.ueq.s $f0,$f2 37 c.olt.s $f0,$f2 38 c.ult.s $f0,$f2 39 c.ole.s $f0,$f2 [all …]
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D | mips-hard-float-flag.s | 3 add.s $f2,$f2,$f2 4 add.d $f2,$f2,$f2 7 add.s $f2,$f2,$f2 8 add.d $f2,$f2,$f2 12 add.s $f2,$f2,$f2 13 add.d $f2,$f2,$f2 16 add.s $f2,$f2,$f2 17 add.d $f2,$f2,$f2
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D | mips-double-float-flag.s | 3 add.s $f2,$f2,$f2 4 add.d $f2,$f2,$f2 7 add.s $f2,$f2,$f2 8 add.d $f2,$f2,$f2 12 add.s $f2,$f2,$f2 13 add.d $f2,$f2,$f2 16 add.s $f2,$f2,$f2 17 add.d $f2,$f2,$f2
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D | r6.s | 3 new: maddf.s $f0,$f1,$f2 7 cmp.af.s $f0,$f1,$f2 8 cmp.af.d $f0,$f1,$f2 9 cmp.un.s $f0,$f1,$f2 10 cmp.un.d $f0,$f1,$f2 11 cmp.eq.s $f0,$f1,$f2 12 cmp.eq.d $f0,$f1,$f2 13 cmp.ueq.s $f0,$f1,$f2 14 cmp.ueq.d $f0,$f1,$f2 15 cmp.lt.s $f0,$f1,$f2 [all …]
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D | msa-branch.s | 10 add.s $f0,$f1,$f2 12 add.s $f0,$f1,$f2 14 add.s $f0,$f1,$f2 16 add.d $f0,$f2,$f4 18 add.d $f0,$f2,$f4 20 add.d $f0,$f2,$f4 29 add.s $f0,$f1,$f2 31 add.s $f0,$f1,$f2 33 add.s $f0,$f1,$f2 35 add.d $f0,$f2,$f4 [all …]
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
D | avx512cd.d | 11 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 f5 vpconflictd %zmm5,%zmm6 12 [ ]*[a-f0-9]+: 62 f2 7d 4f c4 f5 vpconflictd %zmm5,%zmm6\{%k7\} 13 [ ]*[a-f0-9]+: 62 f2 7d cf c4 f5 vpconflictd %zmm5,%zmm6\{%k7\}\{z\} 14 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 31 vpconflictd \(%ecx\),%zmm6 15 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 b4 f4 c0 1d fe ff vpconflictd -0x1e240\(%esp,%esi,8\),%zmm6 16 [ ]*[a-f0-9]+: 62 f2 7d 58 c4 30 vpconflictd \(%eax\)\{1to16\},%zmm6 17 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 7f vpconflictd 0x1fc0\(%edx\),%zmm6 18 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 00 20 00 00 vpconflictd 0x2000\(%edx\),%zmm6 19 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 80 vpconflictd -0x2000\(%edx\),%zmm6 20 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 c0 df ff ff vpconflictd -0x2040\(%edx\),%zmm6 [all …]
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D | avx512er.d | 11 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 f5 vexp2ps %zmm5,%zmm6 12 [ ]*[a-f0-9]+: 62 f2 7d 18 c8 f5 vexp2ps \{sae\},%zmm5,%zmm6 13 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 31 vexp2ps \(%ecx\),%zmm6 14 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 b4 f4 c0 1d fe ff vexp2ps -0x1e240\(%esp,%esi,8\),%zmm6 15 [ ]*[a-f0-9]+: 62 f2 7d 58 c8 30 vexp2ps \(%eax\)\{1to16\},%zmm6 16 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 7f vexp2ps 0x1fc0\(%edx\),%zmm6 17 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 00 20 00 00 vexp2ps 0x2000\(%edx\),%zmm6 18 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 80 vexp2ps -0x2000\(%edx\),%zmm6 19 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 c0 df ff ff vexp2ps -0x2040\(%edx\),%zmm6 20 [ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 7f vexp2ps 0x1fc\(%edx\)\{1to16\},%zmm6 [all …]
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D | avx512cd_vl.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 f5[ ]*vpconflictd %xmm5,%xmm6\{%k7\} 13 [ ]*[a-f0-9]+:[ ]*62 f2 7d 8f c4 f5[ ]*vpconflictd %xmm5,%xmm6\{%k7\}\{z\} 14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 31[ ]*vpconflictd \(%ecx\),%xmm6\{%k7\} 15 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 b4 f4 c0 1d fe ff[ ]*vpconflictd -0x1e240\(%esp,%esi,8\),%xmm6\… 16 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 30[ ]*vpconflictd \(%eax\)\{1to4\},%xmm6\{%k7\} 17 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 72 7f[ ]*vpconflictd 0x7f0\(%edx\),%xmm6\{%k7\} 18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 b2 00 08 00 00[ ]*vpconflictd 0x800\(%edx\),%xmm6\{%k7\} 19 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 72 80[ ]*vpconflictd -0x800\(%edx\),%xmm6\{%k7\} 20 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 b2 f0 f7 ff ff[ ]*vpconflictd -0x810\(%edx\),%xmm6\{%k7\} 21 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 72 7f[ ]*vpconflictd 0x1fc\(%edx\)\{1to4\},%xmm6\{%k7\} [all …]
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D | avx512f_vl-wig1.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 f5[ ]*vpmovsxbd %xmm5,%xmm6\{%k7\} 13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 21 f5[ ]*vpmovsxbd %xmm5,%xmm6\{%k7\}\{z\} 14 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 31[ ]*vpmovsxbd \(%ecx\),%xmm6\{%k7\} 15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd -0x1e240\(%esp,%esi,8\),%xmm6\{%… 16 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 7f[ ]*vpmovsxbd 0x1fc\(%edx\),%xmm6\{%k7\} 17 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%edx\),%xmm6\{%k7\} 18 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd -0x200\(%edx\),%xmm6\{%k7\} 19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 fc fd ff ff[ ]*vpmovsxbd -0x204\(%edx\),%xmm6\{%k7\} 20 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 f5[ ]*vpmovsxbd %xmm5,%ymm6\{%k7\} 21 [ ]*[a-f0-9]+:[ ]*62 f2 fd af 21 f5[ ]*vpmovsxbd %xmm5,%ymm6\{%k7\}\{z\} [all …]
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D | avx512er-intel.d | 12 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 f5 vexp2ps zmm6,zmm5 13 [ ]*[a-f0-9]+: 62 f2 7d 18 c8 f5 vexp2ps zmm6,zmm5,\{sae\} 14 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 31 vexp2ps zmm6,ZMMWORD PTR \[ecx\] 15 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 b4 f4 c0 1d fe ff vexp2ps zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] 16 [ ]*[a-f0-9]+: 62 f2 7d 58 c8 30 vexp2ps zmm6,DWORD PTR \[eax\]\{1to16\} 17 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 7f vexp2ps zmm6,ZMMWORD PTR \[edx\+0x1fc0\] 18 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 00 20 00 00 vexp2ps zmm6,ZMMWORD PTR \[edx\+0x2000\] 19 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 80 vexp2ps zmm6,ZMMWORD PTR \[edx-0x2000\] 20 [ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 c0 df ff ff vexp2ps zmm6,ZMMWORD PTR \[edx-0x2040\] 21 [ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 7f vexp2ps zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\} [all …]
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D | avx512f_vl-wig1-intel.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 f5[ ]*vpmovsxbd xmm6\{k7\},xmm5 13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 21 f5[ ]*vpmovsxbd xmm6\{k7\}\{z\},xmm5 14 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 31[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[ecx\] 15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[esp\+esi\… 16 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 7f[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\] 17 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x200\] 18 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x200\] 19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 fc fd ff ff[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x204\] 20 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 f5[ ]*vpmovsxbd ymm6\{k7\},xmm5 21 [ ]*[a-f0-9]+:[ ]*62 f2 fd af 21 f5[ ]*vpmovsxbd ymm6\{k7\}\{z\},xmm5 [all …]
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D | avx512vbmi_vl.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d f4[ ]*vpermb %xmm4,%xmm5,%xmm6\{%k7\} 13 [ ]*[a-f0-9]+:[ ]*62 f2 55 8f 8d f4[ ]*vpermb %xmm4,%xmm5,%xmm6\{%k7\}\{z\} 14 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 31[ ]*vpermb \(%ecx\),%xmm5,%xmm6\{%k7\} 15 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b4 f4 c0 1d fe ff[ ]*vpermb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6… 16 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 7f[ ]*vpermb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\} 17 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 00 08 00 00[ ]*vpermb 0x800\(%edx\),%xmm5,%xmm6\{%k7\} 18 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 80[ ]*vpermb -0x800\(%edx\),%xmm5,%xmm6\{%k7\} 19 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 f0 f7 ff ff[ ]*vpermb -0x810\(%edx\),%xmm5,%xmm6\{%k7\} 20 [ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d f4[ ]*vpermb %ymm4,%ymm5,%ymm6\{%k7\} 21 [ ]*[a-f0-9]+:[ ]*62 f2 55 af 8d f4[ ]*vpermb %ymm4,%ymm5,%ymm6\{%k7\}\{z\} [all …]
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D | avx512pf.d | 11 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\} 12 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\} 13 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd 0x100\(%eax,%ymm7,1\)\{%k1\} 14 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%ecx,%ymm7,4\)\{%k1\} 15 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\} 16 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\} 17 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 4c 38 40 vgatherpf0dps 0x100\(%eax,%zmm7,1\)\{%k1\} 18 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c b9 00 04 00 00 vgatherpf0dps 0x400\(%ecx,%zmm7,4\)\{%k1\} 19 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\} 20 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\} [all …]
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D | evex-wig1.d | 12 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\} 13 [ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}\{z\} 14 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd \(%ecx\),%zmm6\{%k7\} 15 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b4 f4 c0 1d fe ff vpmovsxbd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\} 16 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 7f vpmovsxbd 0x7f0\(%edx\),%zmm6\{%k7\} 17 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 00 08 00 00 vpmovsxbd 0x800\(%edx\),%zmm6\{%k7\} 18 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 80 vpmovsxbd -0x800\(%edx\),%zmm6\{%k7\} 19 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd -0x810\(%edx\),%zmm6\{%k7\} 20 [ ]*[a-f0-9]+: 62 f2 fd 4f 22 f5 vpmovsxbq %xmm5,%zmm6\{%k7\} 21 [ ]*[a-f0-9]+: 62 f2 fd cf 22 f5 vpmovsxbq %xmm5,%zmm6\{%k7\}\{z\} [all …]
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D | avx512cd-intel.d | 12 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 f5 vpconflictd zmm6,zmm5 13 [ ]*[a-f0-9]+: 62 f2 7d 4f c4 f5 vpconflictd zmm6\{k7\},zmm5 14 [ ]*[a-f0-9]+: 62 f2 7d cf c4 f5 vpconflictd zmm6\{k7\}\{z\},zmm5 15 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 31 vpconflictd zmm6,ZMMWORD PTR \[ecx\] 16 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 b4 f4 c0 1d fe ff vpconflictd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e24… 17 [ ]*[a-f0-9]+: 62 f2 7d 58 c4 30 vpconflictd zmm6,DWORD PTR \[eax\]\{1to16\} 18 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 7f vpconflictd zmm6,ZMMWORD PTR \[edx\+0x1fc0\] 19 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 00 20 00 00 vpconflictd zmm6,ZMMWORD PTR \[edx\+0x2000\] 20 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 80 vpconflictd zmm6,ZMMWORD PTR \[edx-0x2000\] 21 [ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 c0 df ff ff vpconflictd zmm6,ZMMWORD PTR \[edx-0x2040\] [all …]
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D | avx512vbmi.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6 13 [ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6\{%k7\} 14 [ ]*[a-f0-9]+:[ ]*62 f2 55 cf 8d f4[ ]*vpermb %zmm4,%zmm5,%zmm6\{%k7\}\{z\} 15 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 31[ ]*vpermb \(%ecx\),%zmm5,%zmm6 16 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b4 f4 c0 1d fe ff[ ]*vpermb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 17 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 7f[ ]*vpermb 0x1fc0\(%edx\),%zmm5,%zmm6 18 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 00 20 00 00[ ]*vpermb 0x2000\(%edx\),%zmm5,%zmm6 19 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 80[ ]*vpermb -0x2000\(%edx\),%zmm5,%zmm6 20 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 c0 df ff ff[ ]*vpermb -0x2040\(%edx\),%zmm5,%zmm6 21 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 f4[ ]*vpermi2b %zmm4,%zmm5,%zmm6 [all …]
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D | evex-wig1-intel.d | 12 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd zmm6\{k7\},xmm5 13 [ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd zmm6\{k7\}\{z\},xmm5 14 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[ecx\] 15 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b4 f4 c0 1d fe ff vpmovsxbd zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x… 16 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 7f vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] 17 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 00 08 00 00 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x800\] 18 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 80 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx-0x800\] 19 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx-0x810\] 20 [ ]*[a-f0-9]+: 62 f2 fd 4f 22 f5 vpmovsxbq zmm6\{k7\},xmm5 21 [ ]*[a-f0-9]+: 62 f2 fd cf 22 f5 vpmovsxbq zmm6\{k7\}\{z\},xmm5 [all …]
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D | avx512cd_vl-intel.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 f5[ ]*vpconflictd xmm6\{k7\},xmm5 13 [ ]*[a-f0-9]+:[ ]*62 f2 7d 8f c4 f5[ ]*vpconflictd xmm6\{k7\}\{z\},xmm5 14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 31[ ]*vpconflictd xmm6\{k7\},XMMWORD PTR \[ecx\] 15 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 b4 f4 c0 1d fe ff[ ]*vpconflictd xmm6\{k7\},XMMWORD PTR \[esp\+… 16 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 30[ ]*vpconflictd xmm6\{k7\},DWORD PTR \[eax\]\{1to4\} 17 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 72 7f[ ]*vpconflictd xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] 18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 b2 00 08 00 00[ ]*vpconflictd xmm6\{k7\},XMMWORD PTR \[edx\+0x8… 19 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 72 80[ ]*vpconflictd xmm6\{k7\},XMMWORD PTR \[edx-0x800\] 20 [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f c4 b2 f0 f7 ff ff[ ]*vpconflictd xmm6\{k7\},XMMWORD PTR \[edx-0x81… 21 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 72 7f[ ]*vpconflictd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to4\} [all …]
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D | avx512vbmi-intel.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d f4[ ]*vpermb zmm6,zmm5,zmm4 13 [ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8d f4[ ]*vpermb zmm6\{k7\},zmm5,zmm4 14 [ ]*[a-f0-9]+:[ ]*62 f2 55 cf 8d f4[ ]*vpermb zmm6\{k7\}\{z\},zmm5,zmm4 15 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 31[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[ecx\] 16 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b4 f4 c0 1d fe ff[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8… 17 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 7f[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] 18 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 00 20 00 00[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\] 19 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d 72 80[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\] 20 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 8d b2 c0 df ff ff[ ]*vpermb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\] 21 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 75 f4[ ]*vpermi2b zmm6,zmm5,zmm4 [all …]
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D | avx512vbmi_vl-intel.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d f4[ ]*vpermb xmm6\{k7\},xmm5,xmm4 13 [ ]*[a-f0-9]+:[ ]*62 f2 55 8f 8d f4[ ]*vpermb xmm6\{k7\}\{z\},xmm5,xmm4 14 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 31[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\] 15 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b4 f4 c0 1d fe ff[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+… 16 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 7f[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\] 17 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 00 08 00 00[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x8… 18 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d 72 80[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\] 19 [ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8d b2 f0 f7 ff ff[ ]*vpermb xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x81… 20 [ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8d f4[ ]*vpermb ymm6\{k7\},ymm5,ymm4 21 [ ]*[a-f0-9]+:[ ]*62 f2 55 af 8d f4[ ]*vpermb ymm6\{k7\}\{z\},ymm5,ymm4 [all …]
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D | avx512ifma_vl.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 f4[ ]*vpmadd52luq %xmm4,%xmm5,%xmm6\{%k7\} 13 [ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b4 f4[ ]*vpmadd52luq %xmm4,%xmm5,%xmm6\{%k7\}\{z\} 14 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 31[ ]*vpmadd52luq \(%ecx\),%xmm5,%xmm6\{%k7\} 15 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq -0x1e240\(%esp,%esi,8\),%xmm5,… 16 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 30[ ]*vpmadd52luq \(%eax\)\{1to2\},%xmm5,%xmm6\{%k7\} 17 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 7f[ ]*vpmadd52luq 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\} 18 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 00 08 00 00[ ]*vpmadd52luq 0x800\(%edx\),%xmm5,%xmm6\{%k7\} 19 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 80[ ]*vpmadd52luq -0x800\(%edx\),%xmm5,%xmm6\{%k7\} 20 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 f0 f7 ff ff[ ]*vpmadd52luq -0x810\(%edx\),%xmm5,%xmm6\{%k7\} 21 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\} [all …]
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D | avx512pf-intel.d | 12 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\… 13 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\… 14 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\} 15 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]… 16 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\… 17 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\… 18 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 4c 38 40 vgatherpf0dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} 19 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c b9 00 04 00 00 vgatherpf0dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]… 20 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\… 21 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\… [all …]
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D | avx512ifma.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6 13 [ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6\{%k7\} 14 [ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6\{%k7\}\{z\} 15 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 31[ ]*vpmadd52luq \(%ecx\),%zmm5,%zmm6 16 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq -0x1e240\(%esp,%esi,8\),%zmm5,… 17 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 30[ ]*vpmadd52luq \(%eax\)\{1to8\},%zmm5,%zmm6 18 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 7f[ ]*vpmadd52luq 0x1fc0\(%edx\),%zmm5,%zmm6 19 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 00 20 00 00[ ]*vpmadd52luq 0x2000\(%edx\),%zmm5,%zmm6 20 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 80[ ]*vpmadd52luq -0x2000\(%edx\),%zmm5,%zmm6 21 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 c0 df ff ff[ ]*vpmadd52luq -0x2040\(%edx\),%zmm5,%zmm6 [all …]
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D | avx512ifma_vl-intel.d | 12 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 f4[ ]*vpmadd52luq xmm6\{k7\},xmm5,xmm4 13 [ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b4 f4[ ]*vpmadd52luq xmm6\{k7\}\{z\},xmm5,xmm4 14 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 31[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\] 15 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[… 16 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 30[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[eax\]\{1to2\} 17 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 7f[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\] 18 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 00 08 00 00[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx… 19 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 80[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\] 20 [ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 f0 f7 ff ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx… 21 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 7f[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{… [all …]
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D | hle.d | 10 [ ]*[a-f0-9]+: f2 f0 80 11 64 xacquire lock adcb \$0x64,\(%ecx\) 11 [ ]*[a-f0-9]+: f2 f0 80 11 64 xacquire lock adcb \$0x64,\(%ecx\) 14 [ ]*[a-f0-9]+: f0 f2 80 11 64 lock xacquire adcb \$0x64,\(%ecx\) 16 [ ]*[a-f0-9]+: f2 f0 80 01 64 xacquire lock addb \$0x64,\(%ecx\) 17 [ ]*[a-f0-9]+: f2 f0 80 01 64 xacquire lock addb \$0x64,\(%ecx\) 20 [ ]*[a-f0-9]+: f0 f2 80 01 64 lock xacquire addb \$0x64,\(%ecx\) 22 [ ]*[a-f0-9]+: f2 f0 80 21 64 xacquire lock andb \$0x64,\(%ecx\) 23 [ ]*[a-f0-9]+: f2 f0 80 21 64 xacquire lock andb \$0x64,\(%ecx\) 26 [ ]*[a-f0-9]+: f0 f2 80 21 64 lock xacquire andb \$0x64,\(%ecx\) 29 [ ]*[a-f0-9]+: f2 f0 80 09 64 xacquire lock orb \$0x64,\(%ecx\) [all …]
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