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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dx86-64-avx512f_vl-wig1.d12 [ ]*[a-f0-9]+:[ ]*62 02 fd 08 21 f5[ ]*vpmovsxbd %xmm29,%xmm30
13 [ ]*[a-f0-9]+:[ ]*62 02 fd 0f 21 f5[ ]*vpmovsxbd %xmm29,%xmm30\{%k7\}
14 [ ]*[a-f0-9]+:[ ]*62 02 fd 8f 21 f5[ ]*vpmovsxbd %xmm29,%xmm30\{%k7\}\{z\}
15 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 31[ ]*vpmovsxbd \(%rcx\),%xmm30
16 [ ]*[a-f0-9]+:[ ]*62 22 fd 08 21 b4 f0 23 01 00 00[ ]*vpmovsxbd 0x123\(%rax,%r14,8\),%xmm30
17 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 7f[ ]*vpmovsxbd 0x1fc\(%rdx\),%xmm30
18 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%rdx\),%xmm30
19 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 80[ ]*vpmovsxbd -0x200\(%rdx\),%xmm30
20 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 fc fd ff ff[ ]*vpmovsxbd -0x204\(%rdx\),%xmm30
21 [ ]*[a-f0-9]+:[ ]*62 02 fd 28 21 f5[ ]*vpmovsxbd %xmm29,%ymm30
[all …]
Dx86-64-avx512f_vl-wig1-intel.d12 [ ]*[a-f0-9]+:[ ]*62 02 fd 08 21 f5[ ]*vpmovsxbd xmm30,xmm29
13 [ ]*[a-f0-9]+:[ ]*62 02 fd 0f 21 f5[ ]*vpmovsxbd xmm30\{k7\},xmm29
14 [ ]*[a-f0-9]+:[ ]*62 02 fd 8f 21 f5[ ]*vpmovsxbd xmm30\{k7\}\{z\},xmm29
15 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 31[ ]*vpmovsxbd xmm30,DWORD PTR \[rcx\]
16 [ ]*[a-f0-9]+:[ ]*62 22 fd 08 21 b4 f0 23 01 00 00[ ]*vpmovsxbd xmm30,DWORD PTR \[rax\+r14\*8\+0…
17 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 7f[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx\+0x1fc\]
18 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 00 02 00 00[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx\+0x200\]
19 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 80[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx-0x200\]
20 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 fc fd ff ff[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx-0x204\]
21 [ ]*[a-f0-9]+:[ ]*62 02 fd 28 21 f5[ ]*vpmovsxbd ymm30,xmm29
[all …]
Dx86-64-evex-wig1.d12 [ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
13 [ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
14 [ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
15 [ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
16 [ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 23 01 00 00 7b vextractps \$0x7b,%xmm29,0x123\(%rax,%r14,8\)
17 [ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
18 [ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps \$0x7b,%xmm29,0x200\(%rdx\)
19 [ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps \$0x7b,%xmm29,-0x200\(%rdx\)
20 [ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps \$0x7b,%xmm29,-0x204\(%rdx\)
21 [ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}
[all …]
Davx512f_vl-wig1.d12 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 f5[ ]*vpmovsxbd %xmm5,%xmm6\{%k7\}
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 21 f5[ ]*vpmovsxbd %xmm5,%xmm6\{%k7\}\{z\}
14 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 31[ ]*vpmovsxbd \(%ecx\),%xmm6\{%k7\}
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd -0x1e240\(%esp,%esi,8\),%xmm6\{%…
16 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 7f[ ]*vpmovsxbd 0x1fc\(%edx\),%xmm6\{%k7\}
17 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%edx\),%xmm6\{%k7\}
18 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd -0x200\(%edx\),%xmm6\{%k7\}
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 fc fd ff ff[ ]*vpmovsxbd -0x204\(%edx\),%xmm6\{%k7\}
20 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 f5[ ]*vpmovsxbd %xmm5,%ymm6\{%k7\}
21 [ ]*[a-f0-9]+:[ ]*62 f2 fd af 21 f5[ ]*vpmovsxbd %xmm5,%ymm6\{%k7\}\{z\}
[all …]
Dx86-64-evex-wig1-intel.d12 [ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
13 [ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
14 [ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
15 [ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
16 [ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 23 01 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x123\],xm…
17 [ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
18 [ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps DWORD PTR \[rdx\+0x200\],xmm29,0x7b
19 [ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps DWORD PTR \[rdx-0x200\],xmm29,0x7b
20 [ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps DWORD PTR \[rdx-0x204\],xmm29,0x7b
21 [ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd zmm30\{k7\},xmm29
[all …]
Davx512f_vl-wig1-intel.d12 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 f5[ ]*vpmovsxbd xmm6\{k7\},xmm5
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 21 f5[ ]*vpmovsxbd xmm6\{k7\}\{z\},xmm5
14 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 31[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[ecx\]
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b4 f4 c0 1d fe ff[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[esp\+esi\…
16 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 7f[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]
17 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x200\]
18 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x200\]
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 fc fd ff ff[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x204\]
20 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 21 f5[ ]*vpmovsxbd ymm6\{k7\},xmm5
21 [ ]*[a-f0-9]+:[ ]*62 f2 fd af 21 f5[ ]*vpmovsxbd ymm6\{k7\}\{z\},xmm5
[all …]
Davx512pf.d11 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
12 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
13 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
14 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
15 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
16 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
19 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
20 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
21 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 4c 38 20 vgatherpf0qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
22 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c b9 00 04 00 00 vgatherpf0qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
[all …]
Devex-wig1.d12 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}
13 [ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}\{z\}
14 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd \(%ecx\),%zmm6\{%k7\}
15 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b4 f4 c0 1d fe ff vpmovsxbd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
16 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 7f vpmovsxbd 0x7f0\(%edx\),%zmm6\{%k7\}
17 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 00 08 00 00 vpmovsxbd 0x800\(%edx\),%zmm6\{%k7\}
18 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 80 vpmovsxbd -0x800\(%edx\),%zmm6\{%k7\}
19 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd -0x810\(%edx\),%zmm6\{%k7\}
20 [ ]*[a-f0-9]+: 62 f2 fd 4f 22 f5 vpmovsxbq %xmm5,%zmm6\{%k7\}
21 [ ]*[a-f0-9]+: 62 f2 fd cf 22 f5 vpmovsxbq %xmm5,%zmm6\{%k7\}\{z\}
[all …]
Devex-wig1-intel.d12 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd zmm6\{k7\},xmm5
13 [ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd zmm6\{k7\}\{z\},xmm5
14 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[ecx\]
15 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b4 f4 c0 1d fe ff vpmovsxbd zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x…
16 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 7f vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
17 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 00 08 00 00 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
18 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 80 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
19 [ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
20 [ ]*[a-f0-9]+: 62 f2 fd 4f 22 f5 vpmovsxbq zmm6\{k7\},xmm5
21 [ ]*[a-f0-9]+: 62 f2 fd cf 22 f5 vpmovsxbq zmm6\{k7\}\{z\},xmm5
[all …]
Davx512pf-intel.d12 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\…
13 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\…
14 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
15 [ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]…
16 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\…
17 [ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\…
20 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\…
21 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\…
22 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 4c 38 20 vgatherpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
23 [ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]…
[all …]
Dx86-64-avx512cd_vl.d25 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 b2 fc fd ff ff[ ]*vpconflictd -0x204\(%rdx\)\{1to4\},%xmm30
39 [ ]*[a-f0-9]+:[ ]*62 62 7d 38 c4 b2 fc fd ff ff[ ]*vpconflictd -0x204\(%rdx\)\{1to8\},%ymm30
40 [ ]*[a-f0-9]+:[ ]*62 02 fd 08 c4 f5[ ]*vpconflictq %xmm29,%xmm30
41 [ ]*[a-f0-9]+:[ ]*62 02 fd 0f c4 f5[ ]*vpconflictq %xmm29,%xmm30\{%k7\}
42 [ ]*[a-f0-9]+:[ ]*62 02 fd 8f c4 f5[ ]*vpconflictq %xmm29,%xmm30\{%k7\}\{z\}
43 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 c4 31[ ]*vpconflictq \(%rcx\),%xmm30
44 [ ]*[a-f0-9]+:[ ]*62 22 fd 08 c4 b4 f0 23 01 00 00[ ]*vpconflictq 0x123\(%rax,%r14,8\),%xmm30
45 [ ]*[a-f0-9]+:[ ]*62 62 fd 18 c4 31[ ]*vpconflictq \(%rcx\)\{1to2\},%xmm30
46 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 c4 72 7f[ ]*vpconflictq 0x7f0\(%rdx\),%xmm30
47 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 c4 b2 00 08 00 00[ ]*vpconflictq 0x800\(%rdx\),%xmm30
[all …]
Dx86-64-avx512cd.d24 [ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 fc fd ff ff vpconflictd -0x204\(%rdx\)\{1to16\},%zmm30
25 [ ]*[a-f0-9]+: 62 02 fd 48 c4 f5 vpconflictq %zmm29,%zmm30
26 [ ]*[a-f0-9]+: 62 02 fd 4f c4 f5 vpconflictq %zmm29,%zmm30\{%k7\}
27 [ ]*[a-f0-9]+: 62 02 fd cf c4 f5 vpconflictq %zmm29,%zmm30\{%k7\}\{z\}
28 [ ]*[a-f0-9]+: 62 62 fd 48 c4 31 vpconflictq \(%rcx\),%zmm30
29 [ ]*[a-f0-9]+: 62 22 fd 48 c4 b4 f0 23 01 00 00 vpconflictq 0x123\(%rax,%r14,8\),%zmm30
30 [ ]*[a-f0-9]+: 62 62 fd 58 c4 31 vpconflictq \(%rcx\)\{1to8\},%zmm30
31 [ ]*[a-f0-9]+: 62 62 fd 48 c4 72 7f vpconflictq 0x1fc0\(%rdx\),%zmm30
32 [ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 00 20 00 00 vpconflictq 0x2000\(%rdx\),%zmm30
33 [ ]*[a-f0-9]+: 62 62 fd 48 c4 72 80 vpconflictq -0x2000\(%rdx\),%zmm30
[all …]
Dx86-64-avx512cd_vl-intel.d25 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 b2 fc fd ff ff[ ]*vpconflictd xmm30,DWORD PTR \[rdx-0x204\]\{1t…
39 [ ]*[a-f0-9]+:[ ]*62 62 7d 38 c4 b2 fc fd ff ff[ ]*vpconflictd ymm30,DWORD PTR \[rdx-0x204\]\{1t…
40 [ ]*[a-f0-9]+:[ ]*62 02 fd 08 c4 f5[ ]*vpconflictq xmm30,xmm29
41 [ ]*[a-f0-9]+:[ ]*62 02 fd 0f c4 f5[ ]*vpconflictq xmm30\{k7\},xmm29
42 [ ]*[a-f0-9]+:[ ]*62 02 fd 8f c4 f5[ ]*vpconflictq xmm30\{k7\}\{z\},xmm29
43 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 c4 31[ ]*vpconflictq xmm30,XMMWORD PTR \[rcx\]
44 [ ]*[a-f0-9]+:[ ]*62 22 fd 08 c4 b4 f0 23 01 00 00[ ]*vpconflictq xmm30,XMMWORD PTR \[rax\+r14\*…
45 [ ]*[a-f0-9]+:[ ]*62 62 fd 18 c4 31[ ]*vpconflictq xmm30,QWORD PTR \[rcx\]\{1to2\}
46 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 c4 72 7f[ ]*vpconflictq xmm30,XMMWORD PTR \[rdx\+0x7f0\]
47 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 c4 b2 00 08 00 00[ ]*vpconflictq xmm30,XMMWORD PTR \[rdx\+0x800\]
[all …]
Davx512cd.d24 [ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 fc fd ff ff vpconflictd -0x204\(%edx\)\{1to16\},%zmm6
25 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 f5 vpconflictq %zmm5,%zmm6
26 [ ]*[a-f0-9]+: 62 f2 fd 4f c4 f5 vpconflictq %zmm5,%zmm6\{%k7\}
27 [ ]*[a-f0-9]+: 62 f2 fd cf c4 f5 vpconflictq %zmm5,%zmm6\{%k7\}\{z\}
28 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 31 vpconflictq \(%ecx\),%zmm6
29 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 b4 f4 c0 1d fe ff vpconflictq -0x1e240\(%esp,%esi,8\),%zmm6
30 [ ]*[a-f0-9]+: 62 f2 fd 58 c4 30 vpconflictq \(%eax\)\{1to8\},%zmm6
31 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 7f vpconflictq 0x1fc0\(%edx\),%zmm6
32 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 00 20 00 00 vpconflictq 0x2000\(%edx\),%zmm6
33 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 80 vpconflictq -0x2000\(%edx\),%zmm6
[all …]
Davx512cd_vl.d24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 b2 fc fd ff ff[ ]*vpconflictd -0x204\(%edx\)\{1to4\},%xmm6\{%k7…
37 [ ]*[a-f0-9]+:[ ]*62 f2 7d 3f c4 b2 fc fd ff ff[ ]*vpconflictd -0x204\(%edx\)\{1to8\},%ymm6\{%k7…
38 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f c4 f5[ ]*vpconflictq %xmm5,%xmm6\{%k7\}
39 [ ]*[a-f0-9]+:[ ]*62 f2 fd 8f c4 f5[ ]*vpconflictq %xmm5,%xmm6\{%k7\}\{z\}
40 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f c4 31[ ]*vpconflictq \(%ecx\),%xmm6\{%k7\}
41 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f c4 b4 f4 c0 1d fe ff[ ]*vpconflictq -0x1e240\(%esp,%esi,8\),%xmm6\…
42 [ ]*[a-f0-9]+:[ ]*62 f2 fd 1f c4 30[ ]*vpconflictq \(%eax\)\{1to2\},%xmm6\{%k7\}
43 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f c4 72 7f[ ]*vpconflictq 0x7f0\(%edx\),%xmm6\{%k7\}
44 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f c4 b2 00 08 00 00[ ]*vpconflictq 0x800\(%edx\),%xmm6\{%k7\}
45 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f c4 72 80[ ]*vpconflictq -0x800\(%edx\),%xmm6\{%k7\}
[all …]
Dx86-64-avx512cd-intel.d25 [ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 fc fd ff ff vpconflictd zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
26 [ ]*[a-f0-9]+: 62 02 fd 48 c4 f5 vpconflictq zmm30,zmm29
27 [ ]*[a-f0-9]+: 62 02 fd 4f c4 f5 vpconflictq zmm30\{k7\},zmm29
28 [ ]*[a-f0-9]+: 62 02 fd cf c4 f5 vpconflictq zmm30\{k7\}\{z\},zmm29
29 [ ]*[a-f0-9]+: 62 62 fd 48 c4 31 vpconflictq zmm30,ZMMWORD PTR \[rcx\]
30 [ ]*[a-f0-9]+: 62 22 fd 48 c4 b4 f0 23 01 00 00 vpconflictq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x12…
31 [ ]*[a-f0-9]+: 62 62 fd 58 c4 31 vpconflictq zmm30,QWORD PTR \[rcx\]\{1to8\}
32 [ ]*[a-f0-9]+: 62 62 fd 48 c4 72 7f vpconflictq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
33 [ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 00 20 00 00 vpconflictq zmm30,ZMMWORD PTR \[rdx\+0x2000\]
34 [ ]*[a-f0-9]+: 62 62 fd 48 c4 72 80 vpconflictq zmm30,ZMMWORD PTR \[rdx-0x2000\]
[all …]
Dx86-64-avx512er.d23 [ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 fc fd ff ff vexp2ps -0x204\(%rdx\)\{1to16\},%zmm30
24 [ ]*[a-f0-9]+: 62 02 fd 48 c8 f5 vexp2pd %zmm29,%zmm30
25 [ ]*[a-f0-9]+: 62 02 fd 18 c8 f5 vexp2pd \{sae\},%zmm29,%zmm30
26 [ ]*[a-f0-9]+: 62 62 fd 48 c8 31 vexp2pd \(%rcx\),%zmm30
27 [ ]*[a-f0-9]+: 62 22 fd 48 c8 b4 f0 23 01 00 00 vexp2pd 0x123\(%rax,%r14,8\),%zmm30
28 [ ]*[a-f0-9]+: 62 62 fd 58 c8 31 vexp2pd \(%rcx\)\{1to8\},%zmm30
29 [ ]*[a-f0-9]+: 62 62 fd 48 c8 72 7f vexp2pd 0x1fc0\(%rdx\),%zmm30
30 [ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 00 20 00 00 vexp2pd 0x2000\(%rdx\),%zmm30
31 [ ]*[a-f0-9]+: 62 62 fd 48 c8 72 80 vexp2pd -0x2000\(%rdx\),%zmm30
32 [ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 c0 df ff ff vexp2pd -0x2040\(%rdx\),%zmm30
[all …]
Dx86-64-avx512pf.d11 [ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
12 [ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
13 [ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
14 [ ]*[a-f0-9]+: 62 b2 fd 41 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
19 [ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 7b 00 00 00 vgatherpf0qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
20 [ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 7b 00 00 00 vgatherpf0qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
21 [ ]*[a-f0-9]+: 62 92 fd 41 c7 4c 39 20 vgatherpf0qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
22 [ ]*[a-f0-9]+: 62 b2 fd 41 c7 8c b9 00 04 00 00 vgatherpf0qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
27 [ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
28 [ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
[all …]
Davx512cd-intel.d25 [ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 fc fd ff ff vpconflictd zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
26 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 f5 vpconflictq zmm6,zmm5
27 [ ]*[a-f0-9]+: 62 f2 fd 4f c4 f5 vpconflictq zmm6\{k7\},zmm5
28 [ ]*[a-f0-9]+: 62 f2 fd cf c4 f5 vpconflictq zmm6\{k7\}\{z\},zmm5
29 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 31 vpconflictq zmm6,ZMMWORD PTR \[ecx\]
30 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 b4 f4 c0 1d fe ff vpconflictq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e24…
31 [ ]*[a-f0-9]+: 62 f2 fd 58 c4 30 vpconflictq zmm6,QWORD PTR \[eax\]\{1to8\}
32 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 7f vpconflictq zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
33 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 00 20 00 00 vpconflictq zmm6,ZMMWORD PTR \[edx\+0x2000\]
34 [ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 80 vpconflictq zmm6,ZMMWORD PTR \[edx-0x2000\]
[all …]
Dx86-64-avx512f_vl-opts-intel.d12 [ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd xmm30,xmm29
13 [ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s xmm30,xmm29
14 [ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd xmm30\{k7\},xmm29
15 [ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s xmm30\{k7\},xmm29
16 [ ]*[a-f0-9]+:[ ]*62 01 fd 8f 28 f5[ ]*vmovapd xmm30\{k7\}\{z\},xmm29
17 [ ]*[a-f0-9]+:[ ]*62 01 fd 8f 29 ee[ ]*vmovapd\.s xmm30\{k7\}\{z\},xmm29
18 [ ]*[a-f0-9]+:[ ]*62 01 fd 08 28 f5[ ]*vmovapd xmm30,xmm29
19 [ ]*[a-f0-9]+:[ ]*62 01 fd 08 29 ee[ ]*vmovapd\.s xmm30,xmm29
20 [ ]*[a-f0-9]+:[ ]*62 01 fd 0f 28 f5[ ]*vmovapd xmm30\{k7\},xmm29
21 [ ]*[a-f0-9]+:[ ]*62 01 fd 0f 29 ee[ ]*vmovapd\.s xmm30\{k7\},xmm29
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/
Dmvtc.d9 0: fd 77 00 80 mvtc #-128, psw
10 4: fd 77 03 80 mvtc #-128, fpsw
11 8: fd 77 02 80 mvtc #-128, usp
12 c: fd 77 0a 80 mvtc #-128, isp
13 10: fd 77 0c 80 mvtc #-128, intb
14 14: fd 77 08 80 mvtc #-128, bpsw
15 18: fd 77 09 80 mvtc #-128, bpc
16 1c: fd 77 0b 80 mvtc #-128, fintv
17 20: fd 77 00 7f mvtc #127, psw
18 24: fd 77 03 7f mvtc #127, fpsw
[all …]
Dbmcnd.d17 1e: fc fd 02 fc bmc #7, 252\[r0\]\.b
18 22: fc fd f2 fc bmc #7, 252\[r15\]\.b
29 4e: fc fd 02 fc bmc #7, 252\[r0\]\.b
30 52: fc fd f2 fc bmc #7, 252\[r15\]\.b
41 7e: fc fd 00 fc bmeq #7, 252\[r0\]\.b
42 82: fc fd f0 fc bmeq #7, 252\[r15\]\.b
53 ae: fc fd 00 fc bmeq #7, 252\[r0\]\.b
54 b2: fc fd f0 fc bmeq #7, 252\[r15\]\.b
65 de: fc fd 04 fc bmgtu #7, 252\[r0\]\.b
66 e2: fc fd f4 fc bmgtu #7, 252\[r15\]\.b
[all …]
Dstz.d9 0: fd 74 e0 80 stz #-128, r0
10 4: fd 74 ef 80 stz #-128, r15
11 8: fd 74 e0 7f stz #127, r0
12 c: fd 74 ef 7f stz #127, r15
13 10: fd 78 e0 00 80 stz #0xffff8000, r0
14 15: fd 78 ef 00 80 stz #0xffff8000, r15
15 1a: fd 7c e0 00 80 00 stz #0x8000, r0
16 20: fd 7c ef 00 80 00 stz #0x8000, r15
17 26: fd 7c e0 00 00 80 stz #0xff800000, r0
18 2c: fd 7c ef 00 00 80 stz #0xff800000, r15
[all …]
Dstnz.d9 0: fd 74 f0 80 stnz #-128, r0
10 4: fd 74 ff 80 stnz #-128, r15
11 8: fd 74 f0 7f stnz #127, r0
12 c: fd 74 ff 7f stnz #127, r15
13 10: fd 78 f0 00 80 stnz #0xffff8000, r0
14 15: fd 78 ff 00 80 stnz #0xffff8000, r15
15 1a: fd 7c f0 00 80 00 stnz #0x8000, r0
16 20: fd 7c ff 00 80 00 stnz #0x8000, r15
17 26: fd 7c f0 00 00 80 stnz #0xff800000, r0
18 2c: fd 7c ff 00 00 80 stnz #0xff800000, r15
[all …]
Dmvfc.d9 0: fd 6a 00 mvfc psw, r0
10 3: fd 6a 0f mvfc psw, r15
11 6: fd 6a 30 mvfc fpsw, r0
12 9: fd 6a 3f mvfc fpsw, r15
13 c: fd 6a 20 mvfc usp, r0
14 f: fd 6a 2f mvfc usp, r15
15 12: fd 6a a0 mvfc isp, r0
16 15: fd 6a af mvfc isp, r15
17 18: fd 6a c0 mvfc intb, r0
18 1b: fd 6a cf mvfc intb, r15
[all …]

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