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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/
Dpcrel.s22 .half %r_disp16(3b)
23 .half %r_disp16(4f)
25 .half 0
Dpcrel64.s28 .half %r_disp16(3b)
29 .half %r_disp16(4f)
31 .half 0
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dexpected_move_errors.l2 .*:3: Error: Cannot move A1 to low half of register. Input text was A1.
3 .*:4: Error: Cannot move A0 to high half of register. Input text was A0.
Dexpected_errors.l21 .*:27: Error: Cannot move A1 to low half of register. Input text was \).
23 .*:29: Error: Cannot move A0 to high half of register. Input text was \).
96 .*:121: Error: Destination Dregs \(half\) must match.
97 .*:122: Error: Destination Dreg sizes \(full or half\) must match.
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Delf-rel28.s15 ld $4,%half(bar)($4)
37 sd $4,%half(bar)($4)
Dpcrel-2.s4 .half frob-.
Dpcrel-3.s10 .half foo-.
D24k-triple-stores-5.s1 # Mix byte/half/word sizes with arbitary base register.
D24k-triple-stores-5.d3 #name: 24K: Triple Store (Mix byte/half/word size check)
Dmicromips@24k-triple-stores-5.d3 #name: 24K: Triple Store (Mix byte/half/word size check)
Dmips16-hilo-match.s138 .half 0
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-nds32/
Ddiff.s23 .half .L1-.L0
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/
Dvxworks1-lib.s10 lw $28,%half(__GOTT_INDEX__)($28)
/toolchain/binutils/binutils-2.25/cpu/
Dmep-c5.cpu135 (dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
145 (dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
154 (dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
174 (dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
Dlm32.cpu605 (dni sexth "sign extend half-word" ()
894 (dni shgotoff "store half word got offset" (ALIAS)
901 (dni lhgotoff "load half word got offset" (ALIAS)
908 (dni lhugotoff "load half word got offset unsigned" (ALIAS)
Dmep-core.cpu1114 (dnci sh "store half-word (register indirect)" ((STALL STORE))
1142 (dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
1166 (dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
1203 (dnci sh-tp "store half-word (tp relative)" ((STALL STORE))
1231 (dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
1255 (dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
1273 (dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE))
1301 (dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1325 (dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1359 (dnci exth "sign extend half-word" ()
[all …]
Dfrv.cpu251 ; GR set half unit
600 ; GR set half unit
835 ; Media Dual byte to half unit
843 ; Media Dual half to byte unit
851 ; Media Dual byte to half unit extended
1047 ; GR set half unit
1260 ; Media Dual half to byte unit
1424 ; GR set half unit
1644 ; Media Dual half to byte unit
2255 ; General Registers as high and low half words
[all …]
Diq2000.cpu997 (dni lh "load half word" (LOAD-DELAY USES-RS USES-RT)
1008 (dni lhu "load half word unsigned" (LOAD-DELAY USES-RS USES-RT)
1039 (dni sh "store half word" (USES-RS USES-RT)
1092 (dnmi lh-base-0 "load half - implied base 0" (USES-RT NO-DIS)
1176 (dnmi sh-base-0 "store half - implied base 0" (USES-RT NO-DIS)
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-xc16x.texi30 This directive assembles a half-word (8-bit) constant.
Dc-nios2.texi180 @cindex @code{half} directive, Nios II
181 @item .half @var{expression}
Dc-arc.texi303 @cindex @code{half} directive, ARC
304 @item .half @var{expressions}
Dc-nds32.texi269 Push value of half-word variable var into stack.
294 Pop value of half-word variable var from stack using register ra5.
Dc-bfin.texi176 of each register is called the "low" half and is designated with ".L"
178 the "high" half and is designated with ".H" following the name.
Dc-m32c.texi120 modifier is for loading the upper half in such cases. Example:
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/
Dbranch.s16 ; for the next block; half of them will be relaxed.

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