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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dparallel.s21 A1 = Abs a0 || P4 = [fp-4] || r2 = [i1++];
44 R6 = MAX (r5, R2) || r2 = b [p0] (x) || W[i1--]=R0.l;
47 r5 = mIn (r2, R3) || b [p2] = r2 || r0 = [i1++];
48 R4 = Min (r7, R0) || b [p3] = r2 || r1 = [i1++];
51 A0 -= A1 || b [p4] = r2 || r2 = [i1++];
52 a0 -= a1 (w32) || b [p5] = r2 || r3 = [i1++];
54 a0 += a1 || b [sp] = r2 || r4 = [i1++];
55 A0 += A1 (w32) || b [fp] = r2 || r5 = [i1++];
56 r7 = ( a0 += a1) || b [sp] = r3 || r6 = [i1++];
57 r6.l = (A0 += a1) || b [fp] = r3 || r7 = [i1++];
[all …]
Dparallel4.s6 DISAlgnExcpt || [i1] = r0;
9 || [i1++] = r0;
11 [i1--] = r0;
Dparallel2.s19 a1.l = r4.l || r0 = [i1 ++ m3];
20 A0.h = r6.H || r0 = [i1 ++ m2];
21 A1.H = r5.h || r0 = [i1 ++ m1];
22 r0.l = A0 (iu) || r4 = [i1 ++ m0];
Dstore.s28 [i1 ++ m0] = r7;
43 w [i1++] = r7.L;
Dparallel3.s76 R0 = (a0 += r7.l * r6.l), r1 = (a1+= r7.h * r6.h) (ISS2)|| [i1] = r3;
77 r4 = (a0 = r6.l * r7.l), r5 = (a1 += r6.h * r7.h)|| [i1++] = r3;
78 R7 = (A1 += r3.h * r5.H), R6 = (A0 -= r3.l * r5.l)|| [i1--] = r3;
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/all/
Dtest-gen.c119 int i1; member
261 { insn_size_bits, { p1: # name, i1: size, w: bits } } in insn_size_bits()
267 insn_size = arg->i1;
470 { signed_constant, { i1: shift, i2: bits * (revert ? -1 : 1), \ in signed_constant()
495 data->bits = bits << arg->i1;
505 { unsigned_constant, { i1: shift, i2: bits * (revert ? -1 : 1), \ in unsigned_constant()
532 data->bits = bits << arg->i1;
542 { absolute_address, { i1: shift, i2: bits * (revert ? -1 : 1), \ in absolute_address()
570 data->bits = bits << arg->i1;
582 { reg_p, { i1: (shift), p1: (prefix), gen } } in reg_p()
[all …]
Dtest-example.c35 #define jmp_cond(shift) { jmp_cond, { i1: shift } } in jmp_cond()
41 data->bits = val << arg->i1;
/toolchain/binutils/binutils-2.25/gold/testsuite/
Drelro_test.cc39 int i1 = 1; variable
43 int* const p1 __attribute__ ((aligned(64))) = &i1;
59 void* i1addr = static_cast<void*>(&i1); in t1()
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/
Dbz-c.s2 i1 IS #ffff0000ffff0000 label
3 Main BZ $255,i1
Dpushj-c.s2 i1 IS #ffff0000ffff0000 label
3 Main PUSHJ $1,i1
Djump-c.s2 i1 IS #ffff0000ffff0000 label
3 Main JMP i1
Dgeta-c.s2 i1 IS #ffff0000ffff0000 label
3 Main GETA $255,i1
Dpushj-cs.d10 ffff0000ffff0000 l \*ABS\* 0+ i1
Dgeta-c.d10 ffff0000ffff0000 l \*ABS\* 0+ i1
Djump-c.d10 ffff0000ffff0000 l \*ABS\* 0+ i1
Dpushj-c.d10 ffff0000ffff0000 l \*ABS\* 0+ i1
Dbz-c.d10 ffff0000ffff0000 l \*ABS\* 0+ i1
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/
Drelaxation_macro.h11 .irp i1,"\insn1", "\insn2"
13 \i1
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/
Dcbcond.s29 cxbvs %i0, %i1, 1f
31 cwbne %i1, %i2, 1f
32 cwbne %i1, 16, 1f
Dcbcond.d36 68: 1e e6 05 d9 cxbvs %i0, %i1, 0x120
38 70: 32 c6 45 9a cwbne %i1, %i2, 0x120
39 74: 32 c6 65 70 cwbne %i1, 0x10, 0x120
Dhpcvis3.s39 lzcnt %i1, %i2
83 lzd %i1, %i2
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-x86-64/
Ddwarfreloc1.s2 .comm i1,4,4
28 .quad i1 /* DW_AT_location: DW_OP_addr: address */
/toolchain/binutils/binutils-2.25/bfd/
Dcoff-sh.c2194 sh_insns_conflict (unsigned int i1, in sh_insns_conflict() argument
2206 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000) in sh_insns_conflict()
2207 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000)) in sh_insns_conflict()
2220 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1))) in sh_insns_conflict()
2223 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1))) in sh_insns_conflict()
2229 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1))) in sh_insns_conflict()
2232 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1))) in sh_insns_conflict()
2236 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2))) in sh_insns_conflict()
2239 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2))) in sh_insns_conflict()
2242 && sh_insn_uses_or_sets_reg (i1, op1, 0)) in sh_insns_conflict()
[all …]
Delfxx-ia64.c487 bfd_vma t0, t1, i0, i1, i2; in ia64_elf_relax_brl() local
497 i1 = 0x4000000000LL; in ia64_elf_relax_brl()
507 t0 = (i1 << 46) | (i0 << 5) | template_val; in ia64_elf_relax_brl()
508 t1 = (i2 << 23) | (i1 >> 18); in ia64_elf_relax_brl()
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/
Dam33-2.c56 #define freg(shiftlow, shifthigh) { freg, { i1: shiftlow, i2: shifthigh } } in freg()
63 data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2);
73 #define areg(shiftlow, shifthigh) { areg, { i1: shiftlow, i2: shifthigh } } in areg()
80 data->bits = ((data->bits & 3) << arg->i1) | ((data->bits >> 2) << arg->i2);
90 #define dreg(shiftlow, shifthigh) { dreg, { i1: shiftlow, i2: shifthigh } } in dreg()
97 data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2);
108 int diff = insn_size - arg->i1/8 - 1;
153 int diff = insn_size - arg->i1/8 - 1;

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