| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/all/ |
| D | test-gen.c | 120 int i2; member
470 { signed_constant, { i1: shift, i2: bits * (revert ? -1 : 1), \ in signed_constant()
475 int nbits = (arg->i2 >= 0 ? arg->i2 : -arg->i2);
480 if (arg->i2 < 0)
505 { unsigned_constant, { i1: shift, i2: bits * (revert ? -1 : 1), \ in unsigned_constant()
508 int nbits = (arg->i2 >= 0 ? arg->i2 : -arg->i2);
517 if (arg->i2 < 0)
542 { absolute_address, { i1: shift, i2: bits * (revert ? -1 : 1), \ in absolute_address()
545 int nbits = (arg->i2 >= 0 ? arg->i2 : -arg->i2);
555 if (arg->i2 < 0)
[all …]
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| /toolchain/binutils/binutils-2.25/gold/testsuite/ |
| D | relro_test.cc | 40 static int i2 = 2; variable
46 int* const p2 __attribute__ ((aligned(64))) = &i2;
60 void* i2addr = static_cast<void*>(&i2); in t1()
131 *pp1 = &i2; in f2()
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| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | opc2c.c | 370 int i2; in store_opcode_bits() local
374 for (i2 = 0; i2 < 256; i2++) in store_opcode_bits()
375 ind[bits].u.ind[i2].type = T_unused; in store_opcode_bits()
784 int i2; in main() local
788 for (i2 = 0; i2 < opcodes[i]->nbytes; i2++) in main()
789 lprintf (sim_log, " %02x", opcodes[i]->b[i2].decodable_mask); in main()
794 for (i2 = 0; i2 < opcodes[i]->nbytes; i2++) in main()
795 lprintf (sim_log, " %02x", opcodes[i]->b[i2].decodable_bits); in main()
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| D | parallel.s | 26 r4.L = R2.h + r0.L (s) || b [fp] = r0 || r2.H = w [i2--];
30 r4.l = r0 + r1 (RND20) || b [p2] = r0 || R5.l = W [i2--];
88 A1 -= r0.L * R3.H (is) || r2.l = w [i0] || [i2++m2] = R0;
91 r7.l = (a0 = r6.H * r5.L) || r4.l = w [i0] || [i2++m2] = r2;
94 r3.l = (A0 += r7.H * r6.h) (T) || r7.l = w [i0] || [ i2 ++ m2] = R5;
95 r0.l = (a0 -= r3.h * r2.h) || r7.l = w [i1++] || [i2++m2] = r6;
96 r1.l = (a0 -= r5.L * r4.L) (iH) || r6.l = w [i1++] || [i2++m2] = R7;
109 R6 = (a0 -= r2.h * r7.l) || R4.L = W [I2--] || r2.h = w[i2];
113 R5 = (A1 = r2.H * r3.H) (M, fu) || R7.L = W [I2--] || r4.h = W[i2];
119 r7 = -R2(s) || w [p0] = r4.L || r5.l = w[i2++];
[all …]
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| D | parallel4.s | 12 R1 = byteop3p (r1:0, r3:2) (LO, r) || [i2] = r0;
13 r2 = ByteOp3P (r1:0, R3:2) (hi, R) || [i2++] = r0;
15 R5 = A1.l + A1.h, R2 = a0.l + a0.h || [i2--] = r0;
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| D | parallel2.s | 23 R1.H = A1 (s2rnd) || r0 = [i2 ++ m0];
24 r1.h = a1 || r0 = [i2 ++ m1];
25 R2.l = A0, r2.H = A1 (IH) || r0 = [i2 ++ m2];
26 R2.l = A0, r2.H = A1 || r0 = [i2 ++ m3];
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/ |
| D | bz-c.s | 4 BZ $255,i2
5 i2 IS #ffff0000ffff0000 label
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| D | pushj-c.s | 4 PUSHJ $2,i2
5 i2 IS #ffff0000ffff0000 label
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| D | jump-c.s | 4 JMP i2
5 i2 IS #ffff0000ffff0000 label
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| D | geta-c.s | 4 GETA $255,i2
5 i2 IS #ffff0000ffff0000 label
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| D | pushj-cs.d | 11 ffff0000ffff0000 l \*ABS\* 0+ i2
18 4: R_MMIX_PUSHJ_STUBBABLE i2
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| D | geta-c.d | 11 ffff0000ffff0000 l \*ABS\* 0+ i2
23 10: R_MMIX_GETA i2
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| D | jump-c.d | 11 ffff0000ffff0000 l \*ABS\* 0+ i2
24 14: R_MMIX_JMP i2
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| D | pushj-c.d | 11 ffff0000ffff0000 l \*ABS\* 0+ i2
24 14: R_MMIX_PUSHJ i2
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| D | bz-c.d | 11 ffff0000ffff0000 l \*ABS\* 0+ i2
25 18: R_MMIX_CBRANCH i2
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/ |
| D | relaxation_macro.h | 12 .irp i2,"\insn1", "\insn2"
14 \i2
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/ |
| D | cbcond.s | 31 cwbne %i1, %i2, 1f
33 cxbne %i2, %i3, 1f
34 cxbne %i2, 17, 1f
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| D | cbcond.d | 38 70: 32 c6 45 9a cwbne %i1, %i2, 0x120
40 78: 32 e6 85 5b cxbne %i2, %i3, 0x120
41 7c: 32 e6 a5 31 cxbne %i2, 0x11, 0x120
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| D | hpcvis3.s | 39 lzcnt %i1, %i2
83 lzd %i1, %i2
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| D | cfr.s | 7 rd %cfr, %i2
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mt/ |
| D | relocs2.s | 4 .global i2 symbol
5 i2: label
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-x86-64/ |
| D | dwarfreloc2.s | 2 .comm i2,4,4
30 .quad i2 /* DW_AT_location: DW_OP_addr: address */
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| /toolchain/binutils/binutils-2.25/bfd/ |
| D | coff-sh.c | 2196 unsigned int i2, in sh_insns_conflict() argument
2206 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000) in sh_insns_conflict()
2207 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000)) in sh_insns_conflict()
2220 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1))) in sh_insns_conflict()
2223 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1))) in sh_insns_conflict()
2226 && sh_insn_uses_or_sets_reg (i2, op2, 0)) in sh_insns_conflict()
2229 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1))) in sh_insns_conflict()
2232 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1))) in sh_insns_conflict()
2236 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2))) in sh_insns_conflict()
2239 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2))) in sh_insns_conflict()
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/elf/ |
| D | pseudo.s | 7 .internal i2
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| D | am33-2.c | 56 #define freg(shiftlow, shifthigh) { freg, { i1: shiftlow, i2: shifthigh } } in freg()
63 data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2);
73 #define areg(shiftlow, shifthigh) { areg, { i1: shiftlow, i2: shifthigh } } in areg()
80 data->bits = ((data->bits & 3) << arg->i1) | ((data->bits >> 2) << arg->i2);
90 #define dreg(shiftlow, shifthigh) { dreg, { i1: shiftlow, i2: shifthigh } } in dreg()
97 data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2);
|