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Searched refs:ld2w (Results 1 – 23 of 23) sorted by relevance

/toolchain/binutils/binutils-2.25/gas/testsuite/gas/d10v/
Daddress-001.s15 ld2w r0,@r2
24 ld2w r0,@r2+
32 ld2w r0,@r2-
42 ld2w r0,@sp
51 ld2w r0,@sp+
59 ld2w r0,@sp-
73 ld2w r0,@(0x8000,r2)
Daddress-001.d11 4: 70 02 62 04 ld r0, @r2 -> ld2w r0, @r2
14 10: 71 02 e8 05 ld2w r0, @r2\+ -> st r0, @r2\+
16 18: 73 02 ec 05 ld2w r0, @r2- -> st r0, @r2-
19 24: 71 0f 78 1e ld2w r0, @sp -> stb r0, @sp
21 2c: 70 0f e2 1f ld r0, @sp\+ -> ld2w r0, @sp\+
23 34: 72 0f e6 1f ld r0, @sp- -> ld2w r0, @sp-
28 48: f1 02 80 00 ld2w r0, @\(-0x8000, r2\)
Daddress-011.s6 ld2w r0,@+r2
Daddress-040.l3 .*:6: Error: could not assemble: ld2w r0
Daddress-018.s6 ld2w r0,@-r2
Daddress-040.s6 ld2w r0,@-sp
Daddress-018.l3 .*:6: Error: could not assemble: ld2w r0
Daddress-033.l3 .*:6: Error: could not assemble: ld2w r0
Daddress-033.s6 ld2w r0,@+sp
Daddress-011.l3 .*:6: Error: could not assemble: ld2w r0
Dinst.s14 ld2w r0, @0x0800
Dinst.d14 10: f3 01 08 00 ld2w r0, @0x800
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/
Dopt.s84 # serial because ld2w loads r5
85 ld2w r4,@(r0,r6)
88 # serial because ld2w loads r5
89 ld2w r4,@(r0,r6)
92 # parallel even though ld2w uses r6 and adds changes it
93 ld2w r4,@(r0,r6)
97 ld2w r4,@(r0,r6)
101 ld2w r4,@(r0,r6)
Dopt.d36 d0: 04604006 886054d4 ld2w.s r4, @\(r0, r6\) -> adds.s r5, r19, r20
37 d8: 04604006 88603154 ld2w.s r4, @\(r0, r6\) -> adds.s r3, r5, r20
38 e0: 04604006 086064d4 ld2w.s r4, @\(r0, r6\) || adds.s r6, r19, r20
39 e8: 04604006 086074d4 ld2w.s r4, @\(r0, r6\) || adds.s r7, r19, r20
40 f0: 04604006 08607014 ld2w.s r4, @\(r0, r6\) || adds.s r7, r0, r20
68 1a0: 0460e38f 8a610452 ld2w.s r14, @\(r14, r15\) -> mulhxhl r16, r17, r18
Dwarn_oddreg.s2 # of multi-word instructions: ld2w, ld4bh, ld4bhu, ld2h, st2w, st4hb, st2h,
6 ld2w r1, @(r0, 0) || nop label
Dwarn_oddreg.l14 2 # of multi-word instructions: ld2w, ld4bh, ld4bhu, ld2h, st2w, st4hb, st2h,
20 6 0008 04681000 ld2w r1, @(r0, 0) || nop
Dinst.s201 ld2w r6,@(r7,r8)
202 ld2w r6,@(r7+,r8)
203 ld2w r6,@(r7-,r8)
204 ld2w r6,@(r7,0x1a)
205 ld2w r6,@(r7,0x1234)
Dreloc.s50 ld2w r60, @(r0,longzero)
Dinst.d123 388: 046061c8 846461c8 ld2w.s r6, @\(r7, r8\) -> ld2w.s r6, @\(r7\+, r8\)
124 390: 046c61c8 846861da ld2w.s r6, @\(r7-, r8\) -> ld2w.s r6, @\(r7, 0x1a\)
125 398: 846861c0 80001234 ld2w.l r6, @\(r7, 0x1234\)
Dreloc.d72 1018: 846bc000 80001070 ld2w.l r60, @\(r0, 0x1070\)
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-d10v.texi133 @item ld2w r2,@@r8+ || mac a0,r0,r7
135 @item ld2w r2,@@r8+ ||
138 @item ld2w r2,@@r8+
142 @item ld2w r2,@@r8+ ->
/toolchain/binutils/binutils-2.25/opcodes/
DChangeLog-989984 (d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi,
/toolchain/binutils/binutils-2.25/gas/
DChangeLog-9697322 * config/tc-d30v.c (build_insn): Allow odd registers for ld2w and