| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| D | group-reloc-ldc.s | 7 .macro ldctest load store
9 \load 0, c0, [r0, #:pc_g0:(f + 0x214)]
10 \load 0, c0, [r0, #:pc_g1:(f + 0x214)]
11 \load 0, c0, [r0, #:pc_g2:(f + 0x214)]
13 \load 0, c0, [r0, #:sb_g0:(f + 0x214)]
14 \load 0, c0, [r0, #:sb_g1:(f + 0x214)]
15 \load 0, c0, [r0, #:sb_g2:(f + 0x214)]
25 \load 0, c0, [r0, #:pc_g0:(f - 0x214)]
26 \load 0, c0, [r0, #:pc_g1:(f - 0x214)]
27 \load 0, c0, [r0, #:pc_g2:(f - 0x214)]
[all …]
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| D | group-reloc-ldc-encoding-bad.s | 7 .macro ldctest load store cst
9 \load 0, c0, [r0, #:pc_g0:(f + \cst)]
10 \load 0, c0, [r0, #:pc_g1:(f + \cst)]
11 \load 0, c0, [r0, #:pc_g2:(f + \cst)]
13 \load 0, c0, [r0, #:sb_g0:(f + \cst)]
14 \load 0, c0, [r0, #:sb_g1:(f + \cst)]
15 \load 0, c0, [r0, #:sb_g2:(f + \cst)]
25 \load 0, c0, [r0, #:pc_g0:(f - \cst)]
26 \load 0, c0, [r0, #:pc_g1:(f - \cst)]
27 \load 0, c0, [r0, #:pc_g2:(f - \cst)]
[all …]
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| D | group-reloc-ldrs-encoding-bad.s | 5 .macro ldrtest2 load sym offset
7 \load r0, [r0, #:pc_g1:(\sym \offset)]
8 \load r0, [r0, #:pc_g2:(\sym \offset)]
9 \load r0, [r0, #:sb_g0:(\sym \offset)]
10 \load r0, [r0, #:sb_g1:(\sym \offset)]
11 \load r0, [r0, #:sb_g2:(\sym \offset)]
15 .macro ldrtest load store sym offset
17 ldrtest2 \load \sym \offset
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| D | group-reloc-ldrs.s | 5 .macro ldrtest2 load sym offset
7 \load r0, [r0, #:pc_g1:(\sym \offset)]
8 \load r0, [r0, #:pc_g2:(\sym \offset)]
9 \load r0, [r0, #:sb_g0:(\sym \offset)]
10 \load r0, [r0, #:sb_g1:(\sym \offset)]
11 \load r0, [r0, #:sb_g2:(\sym \offset)]
15 .macro ldrtest load store sym offset
17 ldrtest2 \load \sym \offset
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| D | group-reloc-ldr-encoding-bad.s | 6 .macro ldrtest load store sym offset
8 \load r0, [r0, #:pc_g0:(\sym \offset)]
9 \load r0, [r0, #:pc_g1:(\sym \offset)]
10 \load r0, [r0, #:pc_g2:(\sym \offset)]
11 \load r0, [r0, #:sb_g0:(\sym \offset)]
12 \load r0, [r0, #:sb_g1:(\sym \offset)]
13 \load r0, [r0, #:sb_g2:(\sym \offset)]
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| D | group-reloc-ldr.s | 5 .macro ldrtest load store sym offset
7 \load r0, [r0, #:pc_g0:(\sym \offset)]
8 \load r0, [r0, #:pc_g1:(\sym \offset)]
9 \load r0, [r0, #:pc_g2:(\sym \offset)]
10 \load r0, [r0, #:sb_g0:(\sym \offset)]
11 \load r0, [r0, #:sb_g1:(\sym \offset)]
12 \load r0, [r0, #:sb_g2:(\sym \offset)]
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-scripts/ |
| D | overlay-size-map.d | 4 \.bss2 *0x0*20000 *0x30 load address 0x0*20010
6 \.bss3 *0x0*20000 *0x20 load address 0x0*20040
10 \.mtext *0x0*10000 *0x20 load address 0x0*30000
12 \.mbss *0x0*20030 *0x230 load address 0x0*20060
14 \.text1 *0x0*10020 *0x80 load address 0x0*30020
16 \.text2 *0x0*10020 *0x40 load address 0x0*300a0
18 \.text3 *0x0*10020 *0x20 load address 0x0*300e0
22 \.data1 *0x0*20260 *0x30 load address 0x0*30100
24 \.data2 *0x0*20260 *0x40 load address 0x0*30130
26 \.data3 *0x0*20260 *0x50 load address 0x0*30170
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| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | s390-opc.txt | 85 58 l RX_RRRD "load" g5 esa,zarch
86 41 la RX_RRRD "load address" g5 esa,zarch
87 51 lae RX_RRRD "load address extended" g5 esa,zarch
88 9a lam RS_AARD "load access multiple" g5 esa,zarch
89 e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch
90 23 lcdr RR_FF "load complement (long)" g5 esa,zarch
91 33 lcer RR_FF "load complement (short)" g5 esa,zarch
92 13 lcr RR_RR "load complement" g5 esa,zarch
93 b7 lctl RS_CCRD "load control" g5 esa,zarch
94 68 ld RX_FRRD "load (long)" g5 esa,zarch
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic4x/ |
| D | addressing.s | 41 ;; Type C - infix condition load
43 Type_CI:ldiu R0,R0 ; Unconditional load (00000)
44 ldic R0,R0 ; Carry load (00001)
45 ldilo R0,R0 ; Lower than load (00001)
46 ldils R0,R0 ; Lower than or same load (00010)
47 ldihi R0,R0 ; Higher than load (00011)
48 ldihs R0,R0 ; Higher than or same load (00100)
49 ldinc R0,R0 ; No carry load (00100)
50 ldieq R0,R0 ; Equal to load (00101)
51 ldiz R0,R0 ; Zero load (00101)
[all …]
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| /toolchain/binutils/binutils-2.25/gas/doc/ |
| D | c-tilepro.texi | 162 This modifier is used to load the low 16 bits of the symbol's address,
169 This modifier is used to load the high 16 bits of the symbol's
187 This modifier is used to load the offset of the GOT entry
192 This modifier is used to load the sign-extended low 16 bits of the
197 This modifier is used to load the sign-extended high 16 bits of the
220 This modifier is used to load the offset of the GOT entry of the
225 This modifier is used to load the sign-extended low 16 bits of the
231 This modifier is used to load the sign-extended high 16 bits of the
242 This modifier is used to load the offset of the GOT entry containing
248 This modifier is used to load the low 16 bits of the offset of the GOT
[all …]
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| D | c-tilegx.texi | 178 This modifier is used to load bits 0-15 of the symbol's address.
182 This modifier is used to load bits 16-31 of the symbol's address.
186 This modifier is used to load bits 32-47 of the symbol's address.
190 This modifier is used to load bits 48-63 of the symbol's address.
217 This modifier is used to load bits 0-15 of the symbol's offset in the
227 This modifier is used to load bits 16-31 of the symbol's offset in the
246 This modifier is used to load bits 0-15 of the pc-relative address of
251 This modifier is used to load bits 16-31 of the pc-relative address of
261 This modifier is used to load bits 32-47 of the pc-relative address of
266 This modifier is used to load bits 0-15 of the offset of the GOT entry
[all …]
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| /toolchain/binutils/binutils-2.25/cpu/ |
| D | frv.cpu | 97 (prev-fr-load DI) ; Previous use of FR register was target of a load
102 (cur-fr-load DI) ; Current use of FR register was target of a load
259 ; GR load unit
260 (unit u-gr-load "GR Load Unit" ()
275 ; FR load unit
276 (unit u-fr-load "FR Load Unit" ()
608 ; GR load unit -- TODO doesn't handle quad
609 (unit u-gr-load "GR Load Unit" ()
632 ; FR load unit -- TODO doesn't handle quad
633 (unit u-fr-load "FR Load Unit" ()
[all …]
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| D | tls-hidden3a.s | 1 .macro load macro
6 load
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| D | tls-hidden4a.s | 1 .macro load macro
6 load
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| D | tls-hidden3b.s | 1 .macro load macro
14 load
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| D | tls-hidden4b.s | 1 .macro load macro
14 load
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/iq2000/ |
| D | oddldw.s | 1 # This test case includes a single case of a load hazard, whereby an
2 # instruction references a register which is the target of a load.
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| D | oddsdw.s | 1 # This test case includes a single case of a load hazard, whereby an
2 # instruction references a register which is the target of a load.
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| D | hazard5.s | 1 # This test case includes a single case of a load hazard, whereby an
2 # instruction references a register which is the target of a load.
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| D | hazard1.s | 1 # This test case includes a single case of a load hazard, whereby an
2 # instruction references a register which is the target of a load.
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| D | hazard2.s | 1 # This test case includes a single case of a load hazard, whereby an
2 # instruction references a register which is the target of a load.
|
| D | hazard0.s | 1 # This test case includes a single case of a load hazard, whereby an
2 # instruction references a register which is the target of a load.
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| D | hazard4.s | 1 # This test case includes a single case of a load hazard, whereby an
2 # instruction references a register which is the target of a load.
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| D | hazard3.s | 1 # This test case includes a single case of a load hazard, whereby an
2 # instruction references a register which is the target of a load.
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| D | nohazard.s | 1 # This test case includes a number of cases where there is no load
2 # hazard between a load and the instruction which follows it in
|