| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | aarch64-opc.h | 99 int lsb; member
226 ret->lsb = field->lsb + lsb_rel; in gen_sub_field()
238 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0 in insert_field_2()
239 && field->lsb + field->width <= 32); in insert_field_2()
241 value <<= field->lsb; in insert_field_2()
258 value = (code >> field->lsb) & gen_mask (field->width); in extract_field_2()
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| D | v850-opc.c | 568 unsigned long pos,lsb; in extract_POS_U() local
572 lsb = ((insn2 & 0x0800) >> 8) in extract_POS_U()
574 lsb += 16; in extract_POS_U()
575 pos = lsb; in extract_POS_U()
586 unsigned long pos,lsb; in extract_POS_L() local
590 lsb = ((insn2 & 0x0800) >> 8) in extract_POS_L()
592 pos = lsb; in extract_POS_L()
603 unsigned long msb, lsb, opc, ret; in insert_WIDTH() local
607 lsb = G_pos; in insert_WIDTH()
614 if ((msb >= 16) && (lsb >= 16)) in insert_WIDTH()
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| D | aarch64-asm.c | 1007 int64_t lsb, width; in convert_bfx_to_bfm() local
1010 lsb = inst->operands[2].imm.value; in convert_bfx_to_bfm()
1012 inst->operands[2].imm.value = lsb; in convert_bfx_to_bfm()
1013 inst->operands[3].imm.value = lsb + width - 1; in convert_bfx_to_bfm()
1024 int64_t lsb, width; in convert_bfi_to_bfm() local
1027 lsb = inst->operands[2].imm.value; in convert_bfi_to_bfm()
1031 inst->operands[2].imm.value = (32 - lsb) & 0x1f; in convert_bfi_to_bfm()
1036 inst->operands[2].imm.value = (64 - lsb) & 0x3f; in convert_bfi_to_bfm()
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| D | arm-dis.c | 3594 long lsb = (given & 0x00000f80) >> 7; in print_insn_arm() local
3595 long w = msb - lsb + 1; in print_insn_arm()
3598 func (stream, "#%lu, #%lu", lsb, w); in print_insn_arm()
3600 func (stream, "(invalid: %lu:%lu)", lsb, msb); in print_insn_arm()
4284 unsigned int lsb = 0; in print_insn_thumb32() local
4286 lsb |= (given & 0x000000c0u) >> 6; in print_insn_thumb32()
4287 lsb |= (given & 0x00007000u) >> 10; in print_insn_thumb32()
4288 func (stream, "#%u, #%u", lsb, msb - lsb + 1); in print_insn_thumb32()
4295 unsigned int lsb = 0; in print_insn_thumb32() local
4297 lsb |= (given & 0x000000c0u) >> 6; in print_insn_thumb32()
[all …]
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| D | aarch64-dis.c | 1563 int64_t lsb = immr; in convert_bfm_to_bfx() local
1564 inst->operands[2].imm.value = lsb; in convert_bfm_to_bfx()
1565 inst->operands[3].imm.value = imms + 1 - lsb; in convert_bfm_to_bfx()
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| D | ChangeLog-2013 | 1110 individual msb and lsb halves in src1 & src2 fields. Discard the
1111 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
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| D | ChangeLog-9297 | 958 (V_a0): Add macro, lsb of accumulator reg number.
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| D | bitfield-alias.s | 52 .macro bf_32 op, lsb, width
53 \op wzr, w7, #\lsb, #\width
57 .macro bf_64 op, lsb, width
58 \op xzr, x7, #\lsb, #\width
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| D | bitfield-bfm.s | 73 .macro ins2bfm signed, reg, lsb, width
82 .macro x2bfm signed, reg, lsb, width
83 op_bfm signed=\signed, reg=\reg, immr=\lsb, imms="(\lsb+\width-1)"
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| D | order.s | 8 .lsb
21 .lsb
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| D | real.s | 2 .lsb
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| /toolchain/binutils/binutils-2.25/cpu/ |
| D | or1kcommon.cpu | 278 (.apply (.pmacro (group index field msb lsb comment)
290 "SPR field lsb positions"
294 (.apply (.pmacro (group index field msb lsb comment)
295 ((.sym group "-" index "-" field) lsb)
310 (.apply (.pmacro (group index field msb lsb comment)
311 ….splice (.str group "-" index "-" field) (.sll (.inv (.sll (.inv 0) (.add (.sub msb lsb) 1))) lsb))
320 (define-pmacro (define-h-spr-field spr-group spr-index spr-field spr-field-msb spr-field-lsb spr-fi…
329 …ll UWI "@cpu@_h_spr_field_get_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb))
330 …D "@cpu@_h_spr_field_set_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb value))
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| D | mep-core.cpu | 330 ; aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc)
332 ; f-foo-{hi,lo} msb/lsb parts of field f-foo
1020 (define-pmacro (get-rm.lsb) (and rm 1))
1801 (if (get-rm.lsb)
1807 (if (get-rm.lsb)
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/sh64/ |
| D | init64.d | 7 # Make sure that the lsb of DT_INIT and DT_FINI entries is set
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| D | init-media.d | 7 # Make sure that the lsb of DT_INIT and DT_FINI entries is set
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| D | init-cmpct.d | 7 # Make sure that the lsb of DT_INIT and DT_FINI entries is not set
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| /toolchain/binutils/binutils-2.25/include/opcode/ |
| D | mips.h | 495 unsigned short lsb; member
645 insn &= ~(mask << operand->lsb); in mips_insert_operand()
646 insn |= (uval & mask) << operand->lsb; in mips_insert_operand()
655 return (insn >> operand->lsb) & ((1 << operand->size) - 1); in mips_extract_operand()
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| D | ChangeLog | 478 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
479 separately the msb and lsb of a register pair. This is needed to
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| /toolchain/binutils/binutils-2.25/bfd/ |
| D | xsym.c | 1775 long msb, lsb; in bfd_sym_print_type_information() local
1778 bfd_sym_fetch_long (buf, len, offset, &offset, &lsb); in bfd_sym_print_type_information()
1780 fprintf (f, " msb %ld, lsb %ld", msb, lsb); in bfd_sym_print_type_information()
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| D | ChangeLog-0001 | 4189 (hppa_build_one_stub): Mask lsb of plt.offset.
4190 (elf32_hppa_finish_dynamic_symbol): Abort if lsb of plt.offset set.
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| /toolchain/binutils/binutils-2.25/gas/config/ |
| D | tc-mips.c | 3400 used_bits &= ~(1 << (operand->lsb + 5)); in validate_mips_insn()
5021 if (operand_base->lsb == 0 in match_int_operand()
7823 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; in match_insn()
13697 *opcode_extra |= mask << mips_vu0_channel_mask.lsb; in mips_lookup_insn()
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| /toolchain/binutils/binutils-2.25/gas/ |
| D | ChangeLog-2013 | 1668 tic6x_coding_dreg_(msb|lsb) field coding types and use it to
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| /toolchain/binutils/binutils-2.25/gas/testsuite/ |
| D | ChangeLog-9303 | 1637 lsb in SHmedia code addresses.
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