1 /* tc-m32r.c -- Assembler for the Renesas M32R.
2 Copyright (C) 1996-2014 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
20
21 #include "as.h"
22 #include "safe-ctype.h"
23 #include "subsegs.h"
24 #include "symcat.h"
25 #include "opcodes/m32r-desc.h"
26 #include "opcodes/m32r-opc.h"
27 #include "cgen.h"
28 #include "elf/m32r.h"
29
30 /* Linked list of symbols that are debugging symbols to be defined as the
31 beginning of the current instruction. */
32 typedef struct sym_link
33 {
34 struct sym_link *next;
35 symbolS *symbol;
36 } sym_linkS;
37
38 static sym_linkS *debug_sym_link = (sym_linkS *) 0;
39
40 /* Structure to hold all of the different components describing
41 an individual instruction. */
42 typedef struct
43 {
44 const CGEN_INSN *insn;
45 const CGEN_INSN *orig_insn;
46 CGEN_FIELDS fields;
47 #if CGEN_INT_INSN_P
48 CGEN_INSN_INT buffer[1];
49 #define INSN_VALUE(buf) (*(buf))
50 #else
51 unsigned char buffer[CGEN_MAX_INSN_SIZE];
52 #define INSN_VALUE(buf) (buf)
53 #endif
54 char *addr;
55 fragS *frag;
56 int num_fixups;
57 fixS *fixups[GAS_CGEN_MAX_FIXUPS];
58 int indices[MAX_OPERAND_INSTANCES];
59 sym_linkS *debug_sym_link;
60 }
61 m32r_insn;
62
63 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
64 boundary (i.e. was the first of two 16 bit insns). */
65 static m32r_insn prev_insn;
66
67 /* Non-zero if we've seen a relaxable insn since the last 32 bit
68 alignment request. */
69 static int seen_relaxable_p = 0;
70
71 /* Non-zero if we are generating PIC code. */
72 int pic_code;
73
74 /* Non-zero if -relax specified, in which case sufficient relocs are output
75 for the linker to do relaxing.
76 We do simple forms of relaxing internally, but they are always done.
77 This flag does not apply to them. */
78 static int m32r_relax;
79
80 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
81 Each high/shigh reloc must be paired with it's low cousin in order to
82 properly calculate the addend in a relocatable link (since there is a
83 potential carry from the low to the high/shigh).
84 This option is off by default though for user-written assembler code it
85 might make sense to make the default be on (i.e. have gcc pass a flag
86 to turn it off). This warning must not be on for GCC created code as
87 optimization may delete the low but not the high/shigh (at least we
88 shouldn't assume or require it to). */
89 static int warn_unmatched_high = 0;
90
91 /* 1 if -m32rx has been specified, in which case support for
92 the extended M32RX instruction set should be enabled.
93 2 if -m32r2 has been specified, in which case support for
94 the extended M32R2 instruction set should be enabled. */
95 static int enable_m32rx = 0; /* Default to M32R. */
96
97 /* Non-zero if -m32rx -hidden has been specified, in which case support for
98 the special M32RX instruction set should be enabled. */
99 static int enable_special = 0;
100
101 /* Non-zero if -bitinst has been specified, in which case support
102 for extended M32R bit-field instruction set should be enabled. */
103 static int enable_special_m32r = 1;
104
105 /* Non-zero if -float has been specified, in which case support for
106 extended M32R floating point instruction set should be enabled. */
107 static int enable_special_float = 0;
108
109 /* Non-zero if the programmer should be warned when an explicit parallel
110 instruction might have constraint violations. */
111 static int warn_explicit_parallel_conflicts = 1;
112
113 /* Non-zero if the programmer should not receive any messages about
114 parallel instruction with potential or real constraint violations.
115 The ability to suppress these messages is intended only for hardware
116 vendors testing the chip. It superceedes
117 warn_explicit_parallel_conflicts. */
118 static int ignore_parallel_conflicts = 0;
119
120 /* Non-zero if insns can be made parallel. */
121 static int use_parallel = 0;
122
123 /* Non-zero if optimizations should be performed. */
124 static int optimize;
125
126 /* m32r er_flags. */
127 static int m32r_flags = 0;
128
129 /* Stuff for .scomm symbols. */
130 static segT sbss_section;
131 static asection scom_section;
132 static asymbol scom_symbol;
133
134 const char comment_chars[] = ";";
135 const char line_comment_chars[] = "#";
136 const char line_separator_chars[] = "!";
137 const char EXP_CHARS[] = "eE";
138 const char FLT_CHARS[] = "dD";
139
140 /* Relocations against symbols are done in two
141 parts, with a HI relocation and a LO relocation. Each relocation
142 has only 16 bits of space to store an addend. This means that in
143 order for the linker to handle carries correctly, it must be able
144 to locate both the HI and the LO relocation. This means that the
145 relocations must appear in order in the relocation table.
146
147 In order to implement this, we keep track of each unmatched HI
148 relocation. We then sort them so that they immediately precede the
149 corresponding LO relocation. */
150
151 struct m32r_hi_fixup
152 {
153 /* Next HI fixup. */
154 struct m32r_hi_fixup *next;
155
156 /* This fixup. */
157 fixS *fixp;
158
159 /* The section this fixup is in. */
160 segT seg;
161 };
162
163 /* The list of unmatched HI relocs. */
164
165 static struct m32r_hi_fixup *m32r_hi_fixup_list;
166
167 struct
168 {
169 enum bfd_architecture bfd_mach;
170 int mach_flags;
171 } mach_table[] =
172 {
173 { bfd_mach_m32r, (1<<MACH_M32R) },
174 { bfd_mach_m32rx, (1<<MACH_M32RX) },
175 { bfd_mach_m32r2, (1<<MACH_M32R2) }
176 };
177
178 static void
allow_m32rx(int on)179 allow_m32rx (int on)
180 {
181 enable_m32rx = on;
182
183 if (stdoutput != NULL)
184 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
185
186 if (gas_cgen_cpu_desc != NULL)
187 gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
188 }
189
190 #define M32R_SHORTOPTS "O::K:"
191
192 const char *md_shortopts = M32R_SHORTOPTS;
193
194 enum md_option_enums
195 {
196 OPTION_M32R = OPTION_MD_BASE,
197 OPTION_M32RX,
198 OPTION_M32R2,
199 OPTION_BIG,
200 OPTION_LITTLE,
201 OPTION_PARALLEL,
202 OPTION_NO_PARALLEL,
203 OPTION_WARN_PARALLEL,
204 OPTION_NO_WARN_PARALLEL,
205 OPTION_IGNORE_PARALLEL,
206 OPTION_NO_IGNORE_PARALLEL,
207 OPTION_SPECIAL,
208 OPTION_SPECIAL_M32R,
209 OPTION_NO_SPECIAL_M32R,
210 OPTION_SPECIAL_FLOAT,
211 OPTION_WARN_UNMATCHED,
212 OPTION_NO_WARN_UNMATCHED
213 };
214
215 struct option md_longopts[] =
216 {
217 {"m32r", no_argument, NULL, OPTION_M32R},
218 {"m32rx", no_argument, NULL, OPTION_M32RX},
219 {"m32r2", no_argument, NULL, OPTION_M32R2},
220 {"big", no_argument, NULL, OPTION_BIG},
221 {"little", no_argument, NULL, OPTION_LITTLE},
222 {"EB", no_argument, NULL, OPTION_BIG},
223 {"EL", no_argument, NULL, OPTION_LITTLE},
224 {"parallel", no_argument, NULL, OPTION_PARALLEL},
225 {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
226 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
227 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
228 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
229 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
230 {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL},
231 {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL},
232 {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
233 {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
234 {"hidden", no_argument, NULL, OPTION_SPECIAL},
235 {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
236 {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R},
237 {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
238 /* Sigh. I guess all warnings must now have both variants. */
239 {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
240 {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
241 {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
242 {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
243 {NULL, no_argument, NULL, 0}
244 };
245
246 size_t md_longopts_size = sizeof (md_longopts);
247
248 static void
little(int on)249 little (int on)
250 {
251 target_big_endian = ! on;
252 }
253
254 /* Use parallel execution. */
255
256 static int
parallel(void)257 parallel (void)
258 {
259 if (! enable_m32rx)
260 return 0;
261
262 if (use_parallel == 1)
263 return 1;
264
265 return 0;
266 }
267
268 int
md_parse_option(int c,char * arg ATTRIBUTE_UNUSED)269 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
270 {
271 switch (c)
272 {
273 case 'O':
274 optimize = 1;
275 use_parallel = 1;
276 break;
277
278 case OPTION_M32R:
279 allow_m32rx (0);
280 break;
281
282 case OPTION_M32RX:
283 allow_m32rx (1);
284 break;
285
286 case OPTION_M32R2:
287 allow_m32rx (2);
288 enable_special = 1;
289 enable_special_m32r = 1;
290 break;
291
292 case OPTION_BIG:
293 target_big_endian = 1;
294 break;
295
296 case OPTION_LITTLE:
297 target_big_endian = 0;
298 break;
299
300 case OPTION_PARALLEL:
301 use_parallel = 1;
302 break;
303
304 case OPTION_NO_PARALLEL:
305 use_parallel = 0;
306 break;
307
308 case OPTION_WARN_PARALLEL:
309 warn_explicit_parallel_conflicts = 1;
310 break;
311
312 case OPTION_NO_WARN_PARALLEL:
313 warn_explicit_parallel_conflicts = 0;
314 break;
315
316 case OPTION_IGNORE_PARALLEL:
317 ignore_parallel_conflicts = 1;
318 break;
319
320 case OPTION_NO_IGNORE_PARALLEL:
321 ignore_parallel_conflicts = 0;
322 break;
323
324 case OPTION_SPECIAL:
325 if (enable_m32rx)
326 enable_special = 1;
327 else
328 {
329 /* Pretend that we do not recognise this option. */
330 as_bad (_("Unrecognised option: -hidden"));
331 return 0;
332 }
333 break;
334
335 case OPTION_SPECIAL_M32R:
336 enable_special_m32r = 1;
337 break;
338
339 case OPTION_NO_SPECIAL_M32R:
340 enable_special_m32r = 0;
341 break;
342
343 case OPTION_SPECIAL_FLOAT:
344 enable_special_float = 1;
345 break;
346
347 case OPTION_WARN_UNMATCHED:
348 warn_unmatched_high = 1;
349 break;
350
351 case OPTION_NO_WARN_UNMATCHED:
352 warn_unmatched_high = 0;
353 break;
354
355 case 'K':
356 if (strcmp (arg, "PIC") != 0)
357 as_warn (_("Unrecognized option following -K"));
358 else
359 pic_code = 1;
360 break;
361
362 default:
363 return 0;
364 }
365
366 return 1;
367 }
368
369 void
md_show_usage(FILE * stream)370 md_show_usage (FILE *stream)
371 {
372 fprintf (stream, _(" M32R specific command line options:\n"));
373
374 fprintf (stream, _("\
375 -m32r disable support for the m32rx instruction set\n"));
376 fprintf (stream, _("\
377 -m32rx support the extended m32rx instruction set\n"));
378 fprintf (stream, _("\
379 -m32r2 support the extended m32r2 instruction set\n"));
380 fprintf (stream, _("\
381 -EL,-little produce little endian code and data\n"));
382 fprintf (stream, _("\
383 -EB,-big produce big endian code and data\n"));
384 fprintf (stream, _("\
385 -parallel try to combine instructions in parallel\n"));
386 fprintf (stream, _("\
387 -no-parallel disable -parallel\n"));
388 fprintf (stream, _("\
389 -no-bitinst disallow the M32R2's extended bit-field instructions\n"));
390 fprintf (stream, _("\
391 -O try to optimize code. Implies -parallel\n"));
392
393 fprintf (stream, _("\
394 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
395 fprintf (stream, _("\
396 might violate contraints\n"));
397 fprintf (stream, _("\
398 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
399 fprintf (stream, _("\
400 instructions might violate contraints\n"));
401 fprintf (stream, _("\
402 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
403 fprintf (stream, _("\
404 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
405 fprintf (stream, _("\
406 -ignore-parallel-conflicts do not check parallel instructions\n"));
407 fprintf (stream, _("\
408 for constraint violations\n"));
409 fprintf (stream, _("\
410 -no-ignore-parallel-conflicts check parallel instructions for\n"));
411 fprintf (stream, _("\
412 constraint violations\n"));
413 fprintf (stream, _("\
414 -Ip synonym for -ignore-parallel-conflicts\n"));
415 fprintf (stream, _("\
416 -nIp synonym for -no-ignore-parallel-conflicts\n"));
417
418 fprintf (stream, _("\
419 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
420 fprintf (stream, _("\
421 -no-warn-unmatched-high do not warn about missing low relocs\n"));
422 fprintf (stream, _("\
423 -Wuh synonym for -warn-unmatched-high\n"));
424 fprintf (stream, _("\
425 -Wnuh synonym for -no-warn-unmatched-high\n"));
426
427 fprintf (stream, _("\
428 -KPIC generate PIC\n"));
429 }
430
431 /* Set by md_assemble for use by m32r_fill_insn. */
432 static subsegT prev_subseg;
433 static segT prev_seg;
434
435 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
436 symbolS * GOT_symbol;
437
438 static inline int
m32r_PIC_related_p(symbolS * sym)439 m32r_PIC_related_p (symbolS *sym)
440 {
441 expressionS *exp;
442
443 if (! sym)
444 return 0;
445
446 if (sym == GOT_symbol)
447 return 1;
448
449 exp = symbol_get_value_expression (sym);
450
451 return (exp->X_op == O_PIC_reloc
452 || exp->X_md == BFD_RELOC_M32R_26_PLTREL
453 || m32r_PIC_related_p (exp->X_add_symbol)
454 || m32r_PIC_related_p (exp->X_op_symbol));
455 }
456
457 static inline int
m32r_check_fixup(expressionS * main_exp,bfd_reloc_code_real_type * r_type_p)458 m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
459 {
460 expressionS *exp = main_exp;
461
462 if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol))
463 return 1;
464
465 if (exp->X_op == O_symbol && exp->X_add_symbol)
466 {
467 if (exp->X_add_symbol == GOT_symbol)
468 {
469 *r_type_p = BFD_RELOC_M32R_GOTPC24;
470 return 0;
471 }
472 }
473 else if (exp->X_op == O_add)
474 {
475 exp = symbol_get_value_expression (exp->X_add_symbol);
476 if (! exp)
477 return 0;
478 }
479
480 if (exp->X_op == O_PIC_reloc)
481 {
482 *r_type_p = exp->X_md;
483 if (exp == main_exp)
484 exp->X_op = O_symbol;
485 else
486 {
487 main_exp->X_add_symbol = exp->X_add_symbol;
488 main_exp->X_add_number += exp->X_add_number;
489 }
490 }
491 else
492 return (m32r_PIC_related_p (exp->X_add_symbol)
493 || m32r_PIC_related_p (exp->X_op_symbol));
494
495 return 0;
496 }
497
498 /* FIXME: Should be machine generated. */
499 #define NOP_INSN 0x7000
500 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
501
502 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
503 of an rs_align_code fragment. */
504
505 void
m32r_handle_align(fragS * fragp)506 m32r_handle_align (fragS *fragp)
507 {
508 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
509 static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
510
511 int bytes, fix;
512 char *p;
513
514 if (fragp->fr_type != rs_align_code)
515 return;
516
517 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
518 p = fragp->fr_literal + fragp->fr_fix;
519 fix = 0;
520
521 if (bytes & 1)
522 {
523 fix = 1;
524 *p++ = 0;
525 bytes--;
526 }
527
528 if (bytes & 2)
529 {
530 memcpy (p, nop_pattern, 2);
531 p += 2;
532 bytes -= 2;
533 fix += 2;
534 }
535
536 memcpy (p, multi_nop_pattern, 4);
537
538 fragp->fr_fix += fix;
539 fragp->fr_var = 4;
540 }
541
542 /* If the last instruction was the first of 2 16 bit insns,
543 output a nop to move the PC to a 32 bit boundary.
544
545 This is done via an alignment specification since branch relaxing
546 may make it unnecessary.
547
548 Internally, we need to output one of these each time a 32 bit insn is
549 seen after an insn that is relaxable. */
550
551 static void
fill_insn(int ignore ATTRIBUTE_UNUSED)552 fill_insn (int ignore ATTRIBUTE_UNUSED)
553 {
554 frag_align_code (2, 0);
555 prev_insn.insn = NULL;
556 seen_relaxable_p = 0;
557 }
558
559 /* Record the symbol so that when we output the insn, we can create
560 a symbol that is at the start of the instruction. This is used
561 to emit the label for the start of a breakpoint without causing
562 the assembler to emit a NOP if the previous instruction was a
563 16 bit instruction. */
564
565 static void
debug_sym(int ignore ATTRIBUTE_UNUSED)566 debug_sym (int ignore ATTRIBUTE_UNUSED)
567 {
568 char *name;
569 char delim;
570 char *end_name;
571 symbolS *symbolP;
572 sym_linkS *lnk;
573
574 name = input_line_pointer;
575 delim = get_symbol_end ();
576 end_name = input_line_pointer;
577
578 if ((symbolP = symbol_find (name)) == NULL
579 && (symbolP = md_undefined_symbol (name)) == NULL)
580 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
581
582 symbol_table_insert (symbolP);
583 if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
584 || S_IS_EXTERNAL (symbolP)
585 || S_IS_WEAK (symbolP)))
586 /* xgettext:c-format */
587 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
588
589 else
590 {
591 lnk = (sym_linkS *) xmalloc (sizeof (sym_linkS));
592 lnk->symbol = symbolP;
593 lnk->next = debug_sym_link;
594 debug_sym_link = lnk;
595 symbol_get_obj (symbolP)->local = 1;
596 }
597
598 *end_name = delim;
599 demand_empty_rest_of_line ();
600 }
601
602 /* Second pass to expanding the debug symbols, go through linked
603 list of symbols and reassign the address. */
604
605 static void
expand_debug_syms(sym_linkS * syms,int align)606 expand_debug_syms (sym_linkS *syms, int align)
607 {
608 char *save_input_line = input_line_pointer;
609 sym_linkS *next_syms;
610
611 if (!syms)
612 return;
613
614 (void) frag_align_code (align, 0);
615 for (; syms != (sym_linkS *) 0; syms = next_syms)
616 {
617 symbolS *symbolP = syms->symbol;
618 next_syms = syms->next;
619 input_line_pointer = ".\n";
620 pseudo_set (symbolP);
621 free ((char *) syms);
622 }
623
624 input_line_pointer = save_input_line;
625 }
626
627 void
m32r_flush_pending_output(void)628 m32r_flush_pending_output (void)
629 {
630 if (debug_sym_link)
631 {
632 expand_debug_syms (debug_sym_link, 1);
633 debug_sym_link = (sym_linkS *) 0;
634 }
635 }
636
637 /* Cover function to fill_insn called after a label and at end of assembly.
638 The result is always 1: we're called in a conditional to see if the
639 current line is a label. */
640
641 int
m32r_fill_insn(int done)642 m32r_fill_insn (int done)
643 {
644 if (prev_seg != NULL)
645 {
646 segT seg = now_seg;
647 subsegT subseg = now_subseg;
648
649 subseg_set (prev_seg, prev_subseg);
650
651 fill_insn (0);
652
653 subseg_set (seg, subseg);
654 }
655
656 if (done && debug_sym_link)
657 {
658 expand_debug_syms (debug_sym_link, 1);
659 debug_sym_link = (sym_linkS *) 0;
660 }
661
662 return 1;
663 }
664
665 /* The default target format to use. */
666
667 const char *
m32r_target_format(void)668 m32r_target_format (void)
669 {
670 #ifdef TE_LINUX
671 if (target_big_endian)
672 return "elf32-m32r-linux";
673 else
674 return "elf32-m32rle-linux";
675 #else
676 if (target_big_endian)
677 return "elf32-m32r";
678 else
679 return "elf32-m32rle";
680 #endif
681 }
682
683 void
md_begin(void)684 md_begin (void)
685 {
686 flagword applicable;
687 segT seg;
688 subsegT subseg;
689
690 /* Initialize the `cgen' interface. */
691
692 /* Set the machine number and endian. */
693 gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
694 CGEN_CPU_OPEN_ENDIAN,
695 (target_big_endian ?
696 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
697 CGEN_CPU_OPEN_END);
698 m32r_cgen_init_asm (gas_cgen_cpu_desc);
699
700 /* The operand instance table is used during optimization to determine
701 which insns can be executed in parallel. It is also used to give
702 warnings regarding operand interference in parallel insns. */
703 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
704
705 /* This is a callback from cgen to gas to parse operands. */
706 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
707
708 /* Save the current subseg so we can restore it [it's the default one and
709 we don't want the initial section to be .sbss]. */
710 seg = now_seg;
711 subseg = now_subseg;
712
713 /* The sbss section is for local .scomm symbols. */
714 sbss_section = subseg_new (".sbss", 0);
715 seg_info (sbss_section)->bss = 1;
716
717 /* This is copied from perform_an_assembly_pass. */
718 applicable = bfd_applicable_section_flags (stdoutput);
719 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
720
721 subseg_set (seg, subseg);
722
723 /* We must construct a fake section similar to bfd_com_section
724 but with the name .scommon. */
725 scom_section = *bfd_com_section_ptr;
726 scom_section.name = ".scommon";
727 scom_section.output_section = & scom_section;
728 scom_section.symbol = & scom_symbol;
729 scom_section.symbol_ptr_ptr = & scom_section.symbol;
730 scom_symbol = * bfd_com_section_ptr->symbol;
731 scom_symbol.name = ".scommon";
732 scom_symbol.section = & scom_section;
733
734 allow_m32rx (enable_m32rx);
735
736 gas_cgen_initialize_saved_fixups_array ();
737 }
738
739 #define OPERAND_IS_COND_BIT(operand, indices, index) \
740 ((operand)->hw_type == HW_H_COND \
741 || ((operand)->hw_type == HW_H_PSW) \
742 || ((operand)->hw_type == HW_H_CR \
743 && (indices [index] == 0 || indices [index] == 1)))
744
745 /* Returns true if an output of instruction 'a' is referenced by an operand
746 of instruction 'b'. If 'check_outputs' is true then b's outputs are
747 checked, otherwise its inputs are examined. */
748
749 static int
first_writes_to_seconds_operands(m32r_insn * a,m32r_insn * b,const int check_outputs)750 first_writes_to_seconds_operands (m32r_insn *a,
751 m32r_insn *b,
752 const int check_outputs)
753 {
754 const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
755 const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
756 int a_index;
757
758 if (ignore_parallel_conflicts)
759 return 0;
760
761 /* If at least one of the instructions takes no operands, then there is
762 nothing to check. There really are instructions without operands,
763 eg 'nop'. */
764 if (a_operands == NULL || b_ops == NULL)
765 return 0;
766
767 /* Scan the operand list of 'a' looking for an output operand. */
768 for (a_index = 0;
769 a_operands->type != CGEN_OPINST_END;
770 a_index ++, a_operands ++)
771 {
772 if (a_operands->type == CGEN_OPINST_OUTPUT)
773 {
774 int b_index;
775 const CGEN_OPINST *b_operands = b_ops;
776
777 /* Special Case:
778 The Condition bit 'C' is a shadow of the CBR register (control
779 register 1) and also a shadow of bit 31 of the program status
780 word (control register 0). For now this is handled here, rather
781 than by cgen.... */
782
783 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
784 {
785 /* Scan operand list of 'b' looking for another reference to the
786 condition bit, which goes in the right direction. */
787 for (b_index = 0;
788 b_operands->type != CGEN_OPINST_END;
789 b_index++, b_operands++)
790 {
791 if ((b_operands->type
792 == (check_outputs
793 ? CGEN_OPINST_OUTPUT
794 : CGEN_OPINST_INPUT))
795 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
796 return 1;
797 }
798 }
799 else
800 {
801 /* Scan operand list of 'b' looking for an operand that
802 references the same hardware element, and which goes in the
803 right direction. */
804 for (b_index = 0;
805 b_operands->type != CGEN_OPINST_END;
806 b_index++, b_operands++)
807 {
808 if ((b_operands->type
809 == (check_outputs
810 ? CGEN_OPINST_OUTPUT
811 : CGEN_OPINST_INPUT))
812 && (b_operands->hw_type == a_operands->hw_type)
813 && (a->indices[a_index] == b->indices[b_index]))
814 return 1;
815 }
816 }
817 }
818 }
819
820 return 0;
821 }
822
823 /* Returns true if the insn can (potentially) alter the program counter. */
824
825 static int
writes_to_pc(m32r_insn * a)826 writes_to_pc (m32r_insn *a)
827 {
828 if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
829 || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
830 return 1;
831 return 0;
832 }
833
834 /* Return NULL if the two 16 bit insns can be executed in parallel.
835 Otherwise return a pointer to an error message explaining why not. */
836
837 static const char *
can_make_parallel(m32r_insn * a,m32r_insn * b)838 can_make_parallel (m32r_insn *a, m32r_insn *b)
839 {
840 PIPE_ATTR a_pipe;
841 PIPE_ATTR b_pipe;
842
843 /* Make sure the instructions are the right length. */
844 if (CGEN_FIELDS_BITSIZE (&a->fields) != 16
845 || CGEN_FIELDS_BITSIZE (&b->fields) != 16)
846 abort ();
847
848 if (first_writes_to_seconds_operands (a, b, TRUE))
849 return _("instructions write to the same destination register.");
850
851 a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
852 b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
853
854 /* Make sure that the instructions use the correct execution pipelines. */
855 if (a_pipe == PIPE_NONE
856 || b_pipe == PIPE_NONE)
857 return _("Instructions do not use parallel execution pipelines.");
858
859 /* Leave this test for last, since it is the only test that can
860 go away if the instructions are swapped, and we want to make
861 sure that any other errors are detected before this happens. */
862 if (a_pipe == PIPE_S
863 || b_pipe == PIPE_O
864 || (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
865 return _("Instructions share the same execution pipeline");
866
867 return NULL;
868 }
869
870 /* Force the top bit of the second 16-bit insn to be set. */
871
872 static void
make_parallel(CGEN_INSN_BYTES_PTR buffer)873 make_parallel (CGEN_INSN_BYTES_PTR buffer)
874 {
875 #if CGEN_INT_INSN_P
876 *buffer |= 0x8000;
877 #else
878 buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
879 |= 0x80;
880 #endif
881 }
882
883 /* Same as make_parallel except buffer contains the bytes in target order. */
884
885 static void
target_make_parallel(char * buffer)886 target_make_parallel (char *buffer)
887 {
888 buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
889 |= 0x80;
890 }
891
892 /* Assemble two instructions with an explicit parallel operation (||) or
893 sequential operation (->). */
894
895 static void
assemble_two_insns(char * str1,char * str2,int parallel_p)896 assemble_two_insns (char *str1, char *str2, int parallel_p)
897 {
898 char *str3;
899 m32r_insn first;
900 m32r_insn second;
901 char *errmsg;
902 char save_str2 = *str2;
903
904 /* Separate the two instructions. */
905 *str2 = 0;
906
907 /* Make sure the two insns begin on a 32 bit boundary.
908 This is also done for the serial case (foo -> bar), relaxing doesn't
909 affect insns written like this.
910 Note that we must always do this as we can't assume anything about
911 whether we're currently on a 32 bit boundary or not. Relaxing may
912 change this. */
913 fill_insn (0);
914
915 first.debug_sym_link = debug_sym_link;
916 debug_sym_link = (sym_linkS *) 0;
917
918 /* Parse the first instruction. */
919 if (! (first.insn = m32r_cgen_assemble_insn
920 (gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg)))
921 {
922 as_bad ("%s", errmsg);
923 return;
924 }
925
926 /* Check it. */
927 if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
928 {
929 /* xgettext:c-format */
930 as_bad (_("not a 16 bit instruction '%s'"), str1);
931 return;
932 }
933 #ifdef E_M32R2_ARCH
934 else if ((enable_m32rx == 1)
935 /* FIXME: Need standard macro to perform this test. */
936 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
937 & (1 << MACH_M32R2))
938 && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
939 & (1 << MACH_M32RX)))))
940 {
941 /* xgettext:c-format */
942 as_bad (_("instruction '%s' is for the M32R2 only"), str1);
943 return;
944 }
945 else if ((! enable_special
946 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
947 || (! enable_special_m32r
948 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
949 #else
950 else if (! enable_special
951 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
952 #endif
953 {
954 /* xgettext:c-format */
955 as_bad (_("unknown instruction '%s'"), str1);
956 return;
957 }
958 else if (! enable_m32rx
959 /* FIXME: Need standard macro to perform this test. */
960 && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
961 == (1 << MACH_M32RX)))
962 {
963 /* xgettext:c-format */
964 as_bad (_("instruction '%s' is for the M32RX only"), str1);
965 return;
966 }
967
968 /* Check to see if this is an allowable parallel insn. */
969 if (parallel_p
970 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
971 {
972 /* xgettext:c-format */
973 as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
974 return;
975 }
976
977 /* Restore the original assembly text, just in case it is needed. */
978 *str2 = save_str2;
979
980 /* Save the original string pointer. */
981 str3 = str1;
982
983 /* Advanced past the parsed string. */
984 str1 = str2 + 2;
985
986 /* Remember the entire string in case it is needed for error
987 messages. */
988 str2 = str3;
989
990 /* Convert the opcode to lower case. */
991 {
992 char *s2 = str1;
993
994 while (ISSPACE (*s2++))
995 continue;
996
997 --s2;
998
999 while (ISALNUM (*s2))
1000 {
1001 *s2 = TOLOWER (*s2);
1002 s2++;
1003 }
1004 }
1005
1006 /* Preserve any fixups that have been generated and reset the list
1007 to empty. */
1008 gas_cgen_save_fixups (0);
1009
1010 /* Get the indices of the operands of the instruction. */
1011 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
1012 doesn't seem right. Perhaps allow passing fields like we do insn. */
1013 /* FIXME: ALIAS insns do not have operands, so we use this function
1014 to find the equivalent insn and overwrite the value stored in our
1015 structure. We still need the original insn, however, since this
1016 may have certain attributes that are not present in the unaliased
1017 version (eg relaxability). When aliases behave differently this
1018 may have to change. */
1019 first.orig_insn = first.insn;
1020 {
1021 CGEN_FIELDS tmp_fields;
1022 first.insn = cgen_lookup_get_insn_operands
1023 (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
1024 first.indices, &tmp_fields);
1025 }
1026
1027 if (first.insn == NULL)
1028 as_fatal (_("internal error: lookup/get operands failed"));
1029
1030 second.debug_sym_link = NULL;
1031
1032 /* Parse the second instruction. */
1033 if (! (second.insn = m32r_cgen_assemble_insn
1034 (gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg)))
1035 {
1036 as_bad ("%s", errmsg);
1037 return;
1038 }
1039
1040 /* Check it. */
1041 if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
1042 {
1043 /* xgettext:c-format */
1044 as_bad (_("not a 16 bit instruction '%s'"), str1);
1045 return;
1046 }
1047 #ifdef E_M32R2_ARCH
1048 else if ((enable_m32rx == 1)
1049 /* FIXME: Need standard macro to perform this test. */
1050 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
1051 & (1 << MACH_M32R2))
1052 && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
1053 & (1 << MACH_M32RX)))))
1054 {
1055 /* xgettext:c-format */
1056 as_bad (_("instruction '%s' is for the M32R2 only"), str1);
1057 return;
1058 }
1059 else if ((! enable_special
1060 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
1061 || (! enable_special_m32r
1062 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
1063 #else
1064 else if (! enable_special
1065 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
1066 #endif
1067 {
1068 /* xgettext:c-format */
1069 as_bad (_("unknown instruction '%s'"), str1);
1070 return;
1071 }
1072 else if (! enable_m32rx
1073 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
1074 {
1075 /* xgettext:c-format */
1076 as_bad (_("instruction '%s' is for the M32RX only"), str1);
1077 return;
1078 }
1079
1080 /* Check to see if this is an allowable parallel insn. */
1081 if (parallel_p
1082 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
1083 {
1084 /* xgettext:c-format */
1085 as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
1086 return;
1087 }
1088
1089 if (parallel_p && ! enable_m32rx)
1090 {
1091 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
1092 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
1093 {
1094 /* xgettext:c-format */
1095 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
1096 return;
1097 }
1098 }
1099
1100 /* Get the indices of the operands of the instruction. */
1101 second.orig_insn = second.insn;
1102 {
1103 CGEN_FIELDS tmp_fields;
1104 second.insn = cgen_lookup_get_insn_operands
1105 (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
1106 second.indices, &tmp_fields);
1107 }
1108
1109 if (second.insn == NULL)
1110 as_fatal (_("internal error: lookup/get operands failed"));
1111
1112 /* We assume that if the first instruction writes to a register that is
1113 read by the second instruction it is because the programmer intended
1114 this to happen, (after all they have explicitly requested that these
1115 two instructions be executed in parallel). Although if the global
1116 variable warn_explicit_parallel_conflicts is true then we do generate
1117 a warning message. Similarly we assume that parallel branch and jump
1118 instructions are deliberate and should not produce errors. */
1119
1120 if (parallel_p && warn_explicit_parallel_conflicts)
1121 {
1122 if (first_writes_to_seconds_operands (&first, &second, FALSE))
1123 /* xgettext:c-format */
1124 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
1125
1126 if (first_writes_to_seconds_operands (&second, &first, FALSE))
1127 /* xgettext:c-format */
1128 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
1129 }
1130
1131 if (!parallel_p
1132 || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL)
1133 {
1134 /* Get the fixups for the first instruction. */
1135 gas_cgen_swap_fixups (0);
1136
1137 /* Write it out. */
1138 expand_debug_syms (first.debug_sym_link, 1);
1139 gas_cgen_finish_insn (first.orig_insn, first.buffer,
1140 CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
1141
1142 /* Force the top bit of the second insn to be set. */
1143 if (parallel_p)
1144 make_parallel (second.buffer);
1145
1146 /* Get its fixups. */
1147 gas_cgen_restore_fixups (0);
1148
1149 /* Write it out. */
1150 expand_debug_syms (second.debug_sym_link, 1);
1151 gas_cgen_finish_insn (second.orig_insn, second.buffer,
1152 CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
1153 }
1154 /* Try swapping the instructions to see if they work that way. */
1155 else if (can_make_parallel (&second, &first) == NULL)
1156 {
1157 /* Write out the second instruction first. */
1158 expand_debug_syms (second.debug_sym_link, 1);
1159 gas_cgen_finish_insn (second.orig_insn, second.buffer,
1160 CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
1161
1162 /* Force the top bit of the first instruction to be set. */
1163 make_parallel (first.buffer);
1164
1165 /* Get the fixups for the first instruction. */
1166 gas_cgen_restore_fixups (0);
1167
1168 /* Write out the first instruction. */
1169 expand_debug_syms (first.debug_sym_link, 1);
1170 gas_cgen_finish_insn (first.orig_insn, first.buffer,
1171 CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
1172 }
1173 else
1174 {
1175 as_bad ("'%s': %s", str2, errmsg);
1176 return;
1177 }
1178
1179 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
1180 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
1181 m32r_flags |= E_M32R_HAS_HIDDEN_INST;
1182 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
1183 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
1184 m32r_flags |= E_M32R_HAS_BIT_INST;
1185 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
1186 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
1187 m32r_flags |= E_M32R_HAS_FLOAT_INST;
1188
1189 /* Set these so m32r_fill_insn can use them. */
1190 prev_seg = now_seg;
1191 prev_subseg = now_subseg;
1192 }
1193
1194 void
md_assemble(char * str)1195 md_assemble (char *str)
1196 {
1197 m32r_insn insn;
1198 char *errmsg;
1199 char *str2 = NULL;
1200
1201 /* Initialize GAS's cgen interface for a new instruction. */
1202 gas_cgen_init_parse ();
1203
1204 /* Look for a parallel instruction separator. */
1205 if ((str2 = strstr (str, "||")) != NULL)
1206 {
1207 assemble_two_insns (str, str2, 1);
1208 m32r_flags |= E_M32R_HAS_PARALLEL;
1209 return;
1210 }
1211
1212 /* Also look for a sequential instruction separator. */
1213 if ((str2 = strstr (str, "->")) != NULL)
1214 {
1215 assemble_two_insns (str, str2, 0);
1216 return;
1217 }
1218
1219 insn.debug_sym_link = debug_sym_link;
1220 debug_sym_link = (sym_linkS *) 0;
1221
1222 insn.insn = m32r_cgen_assemble_insn
1223 (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
1224
1225 if (!insn.insn)
1226 {
1227 as_bad ("%s", errmsg);
1228 return;
1229 }
1230
1231 #ifdef E_M32R2_ARCH
1232 if ((enable_m32rx == 1)
1233 /* FIXME: Need standard macro to perform this test. */
1234 && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
1235 & (1 << MACH_M32R2))
1236 && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
1237 & (1 << MACH_M32RX)))))
1238 {
1239 /* xgettext:c-format */
1240 as_bad (_("instruction '%s' is for the M32R2 only"), str);
1241 return;
1242 }
1243 else if ((! enable_special
1244 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
1245 || (! enable_special_m32r
1246 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
1247 #else
1248 if (! enable_special
1249 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
1250 #endif
1251 {
1252 /* xgettext:c-format */
1253 as_bad (_("unknown instruction '%s'"), str);
1254 return;
1255 }
1256 else if (! enable_m32rx
1257 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
1258 {
1259 /* xgettext:c-format */
1260 as_bad (_("instruction '%s' is for the M32RX only"), str);
1261 return;
1262 }
1263
1264 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
1265 m32r_flags |= E_M32R_HAS_HIDDEN_INST;
1266 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
1267 m32r_flags |= E_M32R_HAS_BIT_INST;
1268 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
1269 m32r_flags |= E_M32R_HAS_FLOAT_INST;
1270
1271 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
1272 {
1273 /* 32 bit insns must live on 32 bit boundaries. */
1274 if (prev_insn.insn || seen_relaxable_p)
1275 {
1276 /* ??? If calling fill_insn too many times turns us into a memory
1277 pig, can we call a fn to assemble a nop instead of
1278 !seen_relaxable_p? */
1279 fill_insn (0);
1280 }
1281
1282 expand_debug_syms (insn.debug_sym_link, 2);
1283
1284 /* Doesn't really matter what we pass for RELAX_P here. */
1285 gas_cgen_finish_insn (insn.insn, insn.buffer,
1286 CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
1287 }
1288 else
1289 {
1290 int on_32bit_boundary_p;
1291 int swap = FALSE;
1292
1293 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
1294 abort ();
1295
1296 insn.orig_insn = insn.insn;
1297
1298 /* If the previous insn was relaxable, then it may be expanded
1299 to fill the current 16 bit slot. Emit a NOP here to occupy
1300 this slot, so that we can start at optimizing at a 32 bit
1301 boundary. */
1302 if (prev_insn.insn && seen_relaxable_p && optimize)
1303 fill_insn (0);
1304
1305 if (enable_m32rx)
1306 {
1307 /* Get the indices of the operands of the instruction.
1308 FIXME: See assemble_parallel for notes on orig_insn. */
1309 {
1310 CGEN_FIELDS tmp_fields;
1311 insn.insn = cgen_lookup_get_insn_operands
1312 (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
1313 16, insn.indices, &tmp_fields);
1314 }
1315
1316 if (insn.insn == NULL)
1317 as_fatal (_("internal error: lookup/get operands failed"));
1318 }
1319
1320 /* Compute whether we're on a 32 bit boundary or not.
1321 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1322 on_32bit_boundary_p = prev_insn.insn == NULL;
1323
1324 /* Change a frag to, if each insn to swap is in a different frag.
1325 It must keep only one instruction in a frag. */
1326 if (parallel() && on_32bit_boundary_p)
1327 {
1328 frag_wane (frag_now);
1329 frag_new (0);
1330 }
1331
1332 /* Look to see if this instruction can be combined with the
1333 previous instruction to make one, parallel, 32 bit instruction.
1334 If the previous instruction (potentially) changed the flow of
1335 program control, then it cannot be combined with the current
1336 instruction. If the current instruction is relaxable, then it
1337 might be replaced with a longer version, so we cannot combine it.
1338 Also if the output of the previous instruction is used as an
1339 input to the current instruction then it cannot be combined.
1340 Otherwise call can_make_parallel() with both orderings of the
1341 instructions to see if they can be combined. */
1342 if (! on_32bit_boundary_p
1343 && parallel ()
1344 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
1345 && ! writes_to_pc (&prev_insn)
1346 && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
1347 {
1348 if (can_make_parallel (&prev_insn, &insn) == NULL)
1349 make_parallel (insn.buffer);
1350 else if (can_make_parallel (&insn, &prev_insn) == NULL)
1351 swap = TRUE;
1352 }
1353
1354 expand_debug_syms (insn.debug_sym_link, 1);
1355
1356 {
1357 int i;
1358 finished_insnS fi;
1359
1360 /* Ensure each pair of 16 bit insns is in the same frag. */
1361 frag_grow (4);
1362
1363 gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
1364 CGEN_FIELDS_BITSIZE (&insn.fields),
1365 1 /* relax_p */, &fi);
1366 insn.addr = fi.addr;
1367 insn.frag = fi.frag;
1368 insn.num_fixups = fi.num_fixups;
1369 for (i = 0; i < fi.num_fixups; ++i)
1370 insn.fixups[i] = fi.fixups[i];
1371 }
1372
1373 if (swap)
1374 {
1375 int i, tmp;
1376
1377 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1378
1379 /* Swap the two insns */
1380 SWAP_BYTES (prev_insn.addr[0], insn.addr[0]);
1381 SWAP_BYTES (prev_insn.addr[1], insn.addr[1]);
1382
1383 target_make_parallel (insn.addr);
1384
1385 /* Swap any relaxable frags recorded for the two insns. */
1386 /* FIXME: Clarify. relaxation precludes parallel insns */
1387 if (prev_insn.frag->fr_opcode == prev_insn.addr)
1388 prev_insn.frag->fr_opcode = insn.addr;
1389 else if (insn.frag->fr_opcode == insn.addr)
1390 insn.frag->fr_opcode = prev_insn.addr;
1391
1392 /* Change a frag to, if each insn is in a different frag.
1393 It must keep only one instruction in a frag. */
1394 if (prev_insn.frag != insn.frag)
1395 {
1396 for (i = 0; i < prev_insn.num_fixups; ++i)
1397 prev_insn.fixups[i]->fx_frag = insn.frag;
1398 for (i = 0; i < insn.num_fixups; ++i)
1399 insn.fixups[i]->fx_frag = prev_insn.frag;
1400 }
1401 else
1402 {
1403 /* Update the addresses in any fixups.
1404 Note that we don't have to handle the case where each insn is in
1405 a different frag as we ensure they're in the same frag above. */
1406 for (i = 0; i < prev_insn.num_fixups; ++i)
1407 prev_insn.fixups[i]->fx_where += 2;
1408 for (i = 0; i < insn.num_fixups; ++i)
1409 insn.fixups[i]->fx_where -= 2;
1410 }
1411 }
1412
1413 /* Keep track of whether we've seen a pair of 16 bit insns.
1414 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1415 if (on_32bit_boundary_p)
1416 prev_insn = insn;
1417 else
1418 prev_insn.insn = NULL;
1419
1420 /* If the insn needs the following one to be on a 32 bit boundary
1421 (e.g. subroutine calls), fill this insn's slot. */
1422 if (on_32bit_boundary_p
1423 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
1424 fill_insn (0);
1425
1426 /* If this is a relaxable insn (can be replaced with a larger version)
1427 mark the fact so that we can emit an alignment directive for a
1428 following 32 bit insn if we see one. */
1429 if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
1430 seen_relaxable_p = 1;
1431 }
1432
1433 /* Set these so m32r_fill_insn can use them. */
1434 prev_seg = now_seg;
1435 prev_subseg = now_subseg;
1436 }
1437
1438 /* The syntax in the manual says constants begin with '#'.
1439 We just ignore it. */
1440
1441 void
md_operand(expressionS * expressionP)1442 md_operand (expressionS *expressionP)
1443 {
1444 if (*input_line_pointer == '#')
1445 {
1446 input_line_pointer++;
1447 expression (expressionP);
1448 }
1449 }
1450
1451 valueT
md_section_align(segT segment,valueT size)1452 md_section_align (segT segment, valueT size)
1453 {
1454 int align = bfd_get_section_alignment (stdoutput, segment);
1455
1456 return ((size + (1 << align) - 1) & (-1 << align));
1457 }
1458
1459 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)1460 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
1461 {
1462 return 0;
1463 }
1464
1465 /* .scomm pseudo-op handler.
1466
1467 This is a new pseudo-op to handle putting objects in .scommon.
1468 By doing this the linker won't need to do any work,
1469 and more importantly it removes the implicit -G arg necessary to
1470 correctly link the object file. */
1471
1472 static void
m32r_scomm(int ignore ATTRIBUTE_UNUSED)1473 m32r_scomm (int ignore ATTRIBUTE_UNUSED)
1474 {
1475 char *name;
1476 char c;
1477 char *p;
1478 offsetT size;
1479 symbolS *symbolP;
1480 offsetT align;
1481 int align2;
1482
1483 name = input_line_pointer;
1484 c = get_symbol_end ();
1485
1486 /* Just after name is now '\0'. */
1487 p = input_line_pointer;
1488 *p = c;
1489 SKIP_WHITESPACE ();
1490 if (*input_line_pointer != ',')
1491 {
1492 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1493 ignore_rest_of_line ();
1494 return;
1495 }
1496
1497 /* Skip ','. */
1498 input_line_pointer++;
1499 if ((size = get_absolute_expression ()) < 0)
1500 {
1501 /* xgettext:c-format */
1502 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
1503 ignore_rest_of_line ();
1504 return;
1505 }
1506
1507 /* The third argument to .scomm is the alignment. */
1508 if (*input_line_pointer != ',')
1509 align = 8;
1510 else
1511 {
1512 ++input_line_pointer;
1513 align = get_absolute_expression ();
1514 if (align <= 0)
1515 {
1516 as_warn (_("ignoring bad alignment"));
1517 align = 8;
1518 }
1519 }
1520
1521 /* Convert to a power of 2 alignment. */
1522 if (align)
1523 {
1524 for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
1525 continue;
1526 if (align != 1)
1527 {
1528 as_bad (_("Common alignment not a power of 2"));
1529 ignore_rest_of_line ();
1530 return;
1531 }
1532 }
1533 else
1534 align2 = 0;
1535
1536 *p = 0;
1537 symbolP = symbol_find_or_make (name);
1538 *p = c;
1539
1540 if (S_IS_DEFINED (symbolP))
1541 {
1542 /* xgettext:c-format */
1543 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1544 S_GET_NAME (symbolP));
1545 ignore_rest_of_line ();
1546 return;
1547 }
1548
1549 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
1550 {
1551 /* xgettext:c-format */
1552 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1553 S_GET_NAME (symbolP),
1554 (long) S_GET_VALUE (symbolP),
1555 (long) size);
1556
1557 ignore_rest_of_line ();
1558 return;
1559 }
1560
1561 if (symbol_get_obj (symbolP)->local)
1562 {
1563 segT old_sec = now_seg;
1564 int old_subsec = now_subseg;
1565 char *pfrag;
1566
1567 record_alignment (sbss_section, align2);
1568 subseg_set (sbss_section, 0);
1569
1570 if (align2)
1571 frag_align (align2, 0, 0);
1572
1573 if (S_GET_SEGMENT (symbolP) == sbss_section)
1574 symbol_get_frag (symbolP)->fr_symbol = 0;
1575
1576 symbol_set_frag (symbolP, frag_now);
1577
1578 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
1579 (char *) 0);
1580 *pfrag = 0;
1581 S_SET_SIZE (symbolP, size);
1582 S_SET_SEGMENT (symbolP, sbss_section);
1583 S_CLEAR_EXTERNAL (symbolP);
1584 subseg_set (old_sec, old_subsec);
1585 }
1586 else
1587 {
1588 S_SET_VALUE (symbolP, (valueT) size);
1589 S_SET_ALIGN (symbolP, align2);
1590 S_SET_EXTERNAL (symbolP);
1591 S_SET_SEGMENT (symbolP, &scom_section);
1592 }
1593
1594 demand_empty_rest_of_line ();
1595 }
1596
1597 /* The target specific pseudo-ops which we support. */
1598 const pseudo_typeS md_pseudo_table[] =
1599 {
1600 { "word", cons, 4 },
1601 { "fillinsn", fill_insn, 0 },
1602 { "scomm", m32r_scomm, 0 },
1603 { "debugsym", debug_sym, 0 },
1604 { "m32r", allow_m32rx, 0 },
1605 { "m32rx", allow_m32rx, 1 },
1606 { "m32r2", allow_m32rx, 2 },
1607 { "little", little, 1 },
1608 { "big", little, 0 },
1609 { NULL, NULL, 0 }
1610 };
1611
1612 /* Interface to relax_segment. */
1613
1614 /* FIXME: Build table by hand, get it working, then machine generate. */
1615
1616 const relax_typeS md_relax_table[] =
1617 {
1618 /* The fields are:
1619 1) most positive reach of this state,
1620 2) most negative reach of this state,
1621 3) how many bytes this mode will add to the size of the current frag
1622 4) which index into the table to try if we can't fit into this one. */
1623
1624 /* The first entry must be unused because an `rlx_more' value of zero ends
1625 each list. */
1626 {1, 1, 0, 0},
1627
1628 /* The displacement used by GAS is from the end of the 2 byte insn,
1629 so we subtract 2 from the following. */
1630 /* 16 bit insn, 8 bit disp -> 10 bit range.
1631 This doesn't handle a branch in the right slot at the border:
1632 the "& -4" isn't taken into account. It's not important enough to
1633 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1634 case). */
1635 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1636 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1637 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1638 /* Same thing, but with leading nop for alignment. */
1639 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1640 };
1641
1642 long
m32r_relax_frag(segT segment,fragS * fragP,long stretch)1643 m32r_relax_frag (segT segment, fragS *fragP, long stretch)
1644 {
1645 /* Address of branch insn. */
1646 long address = fragP->fr_address + fragP->fr_fix - 2;
1647 long growth = 0;
1648
1649 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1650 if (fragP->fr_subtype == 2)
1651 {
1652 if ((address & 3) != 0)
1653 {
1654 fragP->fr_subtype = 3;
1655 growth = 2;
1656 }
1657 }
1658 else if (fragP->fr_subtype == 3)
1659 {
1660 if ((address & 3) == 0)
1661 {
1662 fragP->fr_subtype = 2;
1663 growth = -2;
1664 }
1665 }
1666 else
1667 {
1668 growth = relax_frag (segment, fragP, stretch);
1669
1670 /* Long jump on odd halfword boundary? */
1671 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1672 {
1673 fragP->fr_subtype = 3;
1674 growth += 2;
1675 }
1676 }
1677
1678 return growth;
1679 }
1680
1681 /* Return an initial guess of the length by which a fragment must grow to
1682 hold a branch to reach its destination.
1683 Also updates fr_type/fr_subtype as necessary.
1684
1685 Called just before doing relaxation.
1686 Any symbol that is now undefined will not become defined.
1687 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1688 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1689 Although it may not be explicit in the frag, pretend fr_var starts
1690 with a 0 value. */
1691
1692 int
md_estimate_size_before_relax(fragS * fragP,segT segment)1693 md_estimate_size_before_relax (fragS *fragP, segT segment)
1694 {
1695 /* The only thing we have to handle here are symbols outside of the
1696 current segment. They may be undefined or in a different segment in
1697 which case linker scripts may place them anywhere.
1698 However, we can't finish the fragment here and emit the reloc as insn
1699 alignment requirements may move the insn about. */
1700 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
1701 || S_IS_EXTERNAL (fragP->fr_symbol)
1702 || S_IS_WEAK (fragP->fr_symbol))
1703 {
1704 /* The symbol is undefined in this segment.
1705 Change the relaxation subtype to the max allowable and leave
1706 all further handling to md_convert_frag. */
1707 fragP->fr_subtype = 2;
1708
1709 {
1710 const CGEN_INSN *insn;
1711 int i;
1712
1713 /* Update the recorded insn.
1714 Fortunately we don't have to look very far.
1715 FIXME: Change this to record in the instruction the next higher
1716 relaxable insn to use. */
1717 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1718 {
1719 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1720 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1721 == 0)
1722 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
1723 break;
1724 }
1725 if (i == 4)
1726 abort ();
1727
1728 fragP->fr_cgen.insn = insn;
1729 return 2;
1730 }
1731 }
1732
1733 return md_relax_table[fragP->fr_subtype].rlx_length;
1734 }
1735
1736 /* *FRAGP has been relaxed to its final size, and now needs to have
1737 the bytes inside it modified to conform to the new size.
1738
1739 Called after relaxation is finished.
1740 fragP->fr_type == rs_machine_dependent.
1741 fragP->fr_subtype is the subtype of what the address relaxed to. */
1742
1743 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,segT sec,fragS * fragP)1744 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1745 segT sec,
1746 fragS *fragP)
1747 {
1748 char *opcode;
1749 char *displacement;
1750 int target_address;
1751 int opcode_address;
1752 int extension;
1753 int addend;
1754
1755 opcode = fragP->fr_opcode;
1756
1757 /* Address opcode resides at in file space. */
1758 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1759
1760 switch (fragP->fr_subtype)
1761 {
1762 case 1:
1763 extension = 0;
1764 displacement = &opcode[1];
1765 break;
1766 case 2:
1767 opcode[0] |= 0x80;
1768 extension = 2;
1769 displacement = &opcode[1];
1770 break;
1771 case 3:
1772 opcode[2] = opcode[0] | 0x80;
1773 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1774 opcode_address += 2;
1775 extension = 4;
1776 displacement = &opcode[3];
1777 break;
1778 default:
1779 abort ();
1780 }
1781
1782 if (S_GET_SEGMENT (fragP->fr_symbol) != sec
1783 || S_IS_EXTERNAL (fragP->fr_symbol)
1784 || S_IS_WEAK (fragP->fr_symbol))
1785 {
1786 /* Symbol must be resolved by linker. */
1787 if (fragP->fr_offset & 3)
1788 as_warn (_("Addend to unresolved symbol not on word boundary."));
1789 #ifdef USE_M32R_OLD_RELOC
1790 addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */
1791 #else
1792 addend = 0;
1793 #endif
1794 }
1795 else
1796 {
1797 /* Address we want to reach in file space. */
1798 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1799 addend = (target_address - (opcode_address & -4)) >> 2;
1800 }
1801
1802 /* Create a relocation for symbols that must be resolved by the linker.
1803 Otherwise output the completed insn. */
1804
1805 if (S_GET_SEGMENT (fragP->fr_symbol) != sec
1806 || S_IS_EXTERNAL (fragP->fr_symbol)
1807 || S_IS_WEAK (fragP->fr_symbol))
1808 {
1809 fixS *fixP;
1810
1811 gas_assert (fragP->fr_subtype != 1);
1812 gas_assert (fragP->fr_cgen.insn != 0);
1813
1814 fixP = gas_cgen_record_fixup (fragP,
1815 /* Offset of branch insn in frag. */
1816 fragP->fr_fix + extension - 4,
1817 fragP->fr_cgen.insn,
1818 4 /* Length. */,
1819 /* FIXME: quick hack. */
1820 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
1821 M32R_OPERAND_DISP24),
1822 fragP->fr_cgen.opinfo,
1823 fragP->fr_symbol, fragP->fr_offset);
1824 if (fragP->fr_cgen.opinfo)
1825 fixP->fx_r_type = fragP->fr_cgen.opinfo;
1826 }
1827
1828 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1829
1830 md_number_to_chars (displacement, (valueT) addend,
1831 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1832
1833 fragP->fr_fix += extension;
1834 }
1835
1836 /* Functions concerning relocs. */
1837
1838 /* The location from which a PC relative jump should be calculated,
1839 given a PC relative reloc. */
1840
1841 long
md_pcrel_from_section(fixS * fixP,segT sec)1842 md_pcrel_from_section (fixS *fixP, segT sec)
1843 {
1844 if (fixP->fx_addsy != (symbolS *) NULL
1845 && (! S_IS_DEFINED (fixP->fx_addsy)
1846 || S_GET_SEGMENT (fixP->fx_addsy) != sec
1847 || S_IS_EXTERNAL (fixP->fx_addsy)
1848 || S_IS_WEAK (fixP->fx_addsy)))
1849 {
1850 if (S_GET_SEGMENT (fixP->fx_addsy) != sec
1851 && S_IS_DEFINED (fixP->fx_addsy)
1852 && ! S_IS_EXTERNAL (fixP->fx_addsy)
1853 && ! S_IS_WEAK (fixP->fx_addsy))
1854 return fixP->fx_offset;
1855
1856 /* The symbol is undefined (or is defined but not in this section).
1857 Let the linker figure it out. */
1858 return 0;
1859 }
1860
1861 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1862 }
1863
1864 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1865 Returns BFD_RELOC_NONE if no reloc type can be found.
1866 *FIXP may be modified if desired. */
1867
1868 bfd_reloc_code_real_type
md_cgen_lookup_reloc(const CGEN_INSN * insn ATTRIBUTE_UNUSED,const CGEN_OPERAND * operand,fixS * fixP)1869 md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
1870 const CGEN_OPERAND *operand,
1871 fixS *fixP)
1872 {
1873 switch (operand->type)
1874 {
1875 case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL;
1876 case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL;
1877 case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL;
1878 case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24;
1879 case M32R_OPERAND_HI16:
1880 case M32R_OPERAND_SLO16:
1881 case M32R_OPERAND_ULO16:
1882 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1883 if (fixP->fx_cgen.opinfo != 0)
1884 return fixP->fx_cgen.opinfo;
1885 break;
1886 default:
1887 /* Avoid -Wall warning. */
1888 break;
1889 }
1890 return BFD_RELOC_NONE;
1891 }
1892
1893 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1894
1895 static void
m32r_record_hi16(int reloc_type,fixS * fixP,segT seg ATTRIBUTE_UNUSED)1896 m32r_record_hi16 (int reloc_type,
1897 fixS *fixP,
1898 segT seg ATTRIBUTE_UNUSED)
1899 {
1900 struct m32r_hi_fixup *hi_fixup;
1901
1902 gas_assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1903 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1904
1905 hi_fixup = xmalloc (sizeof (* hi_fixup));
1906 hi_fixup->fixp = fixP;
1907 hi_fixup->seg = now_seg;
1908 hi_fixup->next = m32r_hi_fixup_list;
1909
1910 m32r_hi_fixup_list = hi_fixup;
1911 }
1912
1913 /* Called while parsing an instruction to create a fixup.
1914 We need to check for HI16 relocs and queue them up for later sorting. */
1915
1916 fixS *
m32r_cgen_record_fixup_exp(fragS * frag,int where,const CGEN_INSN * insn,int length,const CGEN_OPERAND * operand,int opinfo,expressionS * exp)1917 m32r_cgen_record_fixup_exp (fragS *frag,
1918 int where,
1919 const CGEN_INSN *insn,
1920 int length,
1921 const CGEN_OPERAND *operand,
1922 int opinfo,
1923 expressionS *exp)
1924 {
1925 fixS *fixP;
1926 bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
1927
1928 if (m32r_check_fixup (exp, &r_type))
1929 as_bad (_("Invalid PIC expression."));
1930
1931 fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
1932 operand, opinfo, exp);
1933
1934 switch (operand->type)
1935 {
1936 case M32R_OPERAND_HI16:
1937 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1938 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
1939 || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
1940 m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
1941 break;
1942
1943 default:
1944 /* Avoid -Wall warning. */
1945 break;
1946 }
1947
1948 switch (r_type)
1949 {
1950 case BFD_RELOC_UNUSED:
1951 default:
1952 return fixP;
1953
1954 case BFD_RELOC_M32R_GOTPC24:
1955 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
1956 r_type = BFD_RELOC_M32R_GOTPC_HI_SLO;
1957 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
1958 r_type = BFD_RELOC_M32R_GOTPC_HI_ULO;
1959 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
1960 r_type = BFD_RELOC_M32R_GOTPC_LO;
1961 break;
1962
1963 case BFD_RELOC_M32R_GOT24:
1964 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
1965 r_type = BFD_RELOC_M32R_GOT16_HI_SLO;
1966 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
1967 r_type = BFD_RELOC_M32R_GOT16_HI_ULO;
1968 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
1969 r_type = BFD_RELOC_M32R_GOT16_LO;
1970 break;
1971
1972 case BFD_RELOC_M32R_GOTOFF:
1973 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
1974 r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO;
1975 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
1976 r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO;
1977 else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
1978 r_type = BFD_RELOC_M32R_GOTOFF_LO;
1979 break;
1980
1981 case BFD_RELOC_M32R_26_PLTREL:
1982 as_bad (_("Invalid PIC expression."));
1983 break;
1984 }
1985
1986 fixP->fx_r_type = r_type;
1987
1988 return fixP;
1989 }
1990
1991 /* Return BFD reloc type from opinfo field in a fixS.
1992 It's tricky using fx_r_type in m32r_frob_file because the values
1993 are BFD_RELOC_UNUSED + operand number. */
1994 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1995
1996 /* Sort any unmatched HI16 relocs so that they immediately precede
1997 the corresponding LO16 reloc. This is called before md_apply_fix and
1998 tc_gen_reloc. */
1999
2000 void
m32r_frob_file(void)2001 m32r_frob_file (void)
2002 {
2003 struct m32r_hi_fixup *l;
2004
2005 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
2006 {
2007 segment_info_type *seginfo;
2008 int pass;
2009
2010 gas_assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
2011 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
2012
2013 /* Check quickly whether the next fixup happens to be a matching low. */
2014 if (l->fixp->fx_next != NULL
2015 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
2016 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
2017 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
2018 continue;
2019
2020 /* Look through the fixups for this segment for a matching `low'.
2021 When we find one, move the high/shigh just in front of it. We do
2022 this in two passes. In the first pass, we try to find a
2023 unique `low'. In the second pass, we permit multiple high's
2024 relocs for a single `low'. */
2025 seginfo = seg_info (l->seg);
2026 for (pass = 0; pass < 2; pass++)
2027 {
2028 fixS *f;
2029 fixS *prev;
2030
2031 prev = NULL;
2032 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
2033 {
2034 /* Check whether this is a `low' fixup which matches l->fixp. */
2035 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
2036 && f->fx_addsy == l->fixp->fx_addsy
2037 && f->fx_offset == l->fixp->fx_offset
2038 && (pass == 1
2039 || prev == NULL
2040 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
2041 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
2042 || prev->fx_addsy != f->fx_addsy
2043 || prev->fx_offset != f->fx_offset))
2044 {
2045 fixS **pf;
2046
2047 /* Move l->fixp before f. */
2048 for (pf = &seginfo->fix_root;
2049 *pf != l->fixp;
2050 pf = & (*pf)->fx_next)
2051 gas_assert (*pf != NULL);
2052
2053 *pf = l->fixp->fx_next;
2054
2055 l->fixp->fx_next = f;
2056 if (prev == NULL)
2057 seginfo->fix_root = l->fixp;
2058 else
2059 prev->fx_next = l->fixp;
2060
2061 break;
2062 }
2063
2064 prev = f;
2065 }
2066
2067 if (f != NULL)
2068 break;
2069
2070 if (pass == 1
2071 && warn_unmatched_high)
2072 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
2073 _("Unmatched high/shigh reloc"));
2074 }
2075 }
2076 }
2077
2078 /* See whether we need to force a relocation into the output file.
2079 This is used to force out switch and PC relative relocations when
2080 relaxing. */
2081
2082 int
m32r_force_relocation(fixS * fix)2083 m32r_force_relocation (fixS *fix)
2084 {
2085 if (generic_force_reloc (fix))
2086 return 1;
2087
2088 if (! m32r_relax)
2089 return 0;
2090
2091 return fix->fx_pcrel;
2092 }
2093
2094 /* Write a value out to the object file, using the appropriate endianness. */
2095
2096 void
md_number_to_chars(char * buf,valueT val,int n)2097 md_number_to_chars (char *buf, valueT val, int n)
2098 {
2099 if (target_big_endian)
2100 number_to_chars_bigendian (buf, val, n);
2101 else
2102 number_to_chars_littleendian (buf, val, n);
2103 }
2104
2105 /* Turn a string in input_line_pointer into a floating point constant
2106 of type TYPE, and store the appropriate bytes in *LITP. The number
2107 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2108 returned, or NULL on OK. */
2109
2110 /* Equal to MAX_PRECISION in atof-ieee.c. */
2111 #define MAX_LITTLENUMS 6
2112
2113 char *
md_atof(int type,char * litP,int * sizeP)2114 md_atof (int type, char *litP, int *sizeP)
2115 {
2116 return ieee_md_atof (type, litP, sizeP, target_big_endian);
2117 }
2118
2119 void
m32r_elf_section_change_hook(void)2120 m32r_elf_section_change_hook (void)
2121 {
2122 /* If we have reached the end of a section and we have just emitted a
2123 16 bit insn, then emit a nop to make sure that the section ends on
2124 a 32 bit boundary. */
2125
2126 if (prev_insn.insn || seen_relaxable_p)
2127 (void) m32r_fill_insn (0);
2128 }
2129
2130 /* Return true if can adjust the reloc to be relative to its section
2131 (such as .data) instead of relative to some symbol. */
2132
2133 bfd_boolean
m32r_fix_adjustable(fixS * fixP)2134 m32r_fix_adjustable (fixS *fixP)
2135 {
2136 bfd_reloc_code_real_type reloc_type;
2137
2138 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
2139 {
2140 const CGEN_INSN *insn = NULL;
2141 int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
2142 const CGEN_OPERAND *operand =
2143 cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
2144
2145 reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
2146 }
2147 else
2148 reloc_type = fixP->fx_r_type;
2149
2150 if (fixP->fx_addsy == NULL)
2151 return 1;
2152
2153 /* Prevent all adjustments to global symbols. */
2154 if (S_IS_EXTERNAL (fixP->fx_addsy))
2155 return 0;
2156 if (S_IS_WEAK (fixP->fx_addsy))
2157 return 0;
2158
2159 if (pic_code
2160 && (reloc_type == BFD_RELOC_M32R_24
2161 || reloc_type == BFD_RELOC_M32R_26_PCREL
2162 || reloc_type == BFD_RELOC_M32R_HI16_SLO
2163 || reloc_type == BFD_RELOC_M32R_HI16_ULO
2164 || reloc_type == BFD_RELOC_M32R_LO16))
2165 return 0;
2166
2167 if (reloc_type == BFD_RELOC_M32R_GOT24
2168 || reloc_type == BFD_RELOC_M32R_26_PLTREL
2169 || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO
2170 || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO
2171 || reloc_type == BFD_RELOC_M32R_GOTPC_LO
2172 || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO
2173 || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO
2174 || reloc_type == BFD_RELOC_M32R_GOT16_LO)
2175 return 0;
2176
2177 /* We need the symbol name for the VTABLE entries. */
2178 if (reloc_type == BFD_RELOC_VTABLE_INHERIT
2179 || reloc_type == BFD_RELOC_VTABLE_ENTRY)
2180 return 0;
2181
2182 return 1;
2183 }
2184
2185 void
m32r_elf_final_processing(void)2186 m32r_elf_final_processing (void)
2187 {
2188 if (use_parallel)
2189 m32r_flags |= E_M32R_HAS_PARALLEL;
2190 elf_elfheader (stdoutput)->e_flags |= m32r_flags;
2191 }
2192
2193 /* Translate internal representation of relocation info to BFD target
2194 format. */
2195
2196 arelent *
tc_gen_reloc(asection * section,fixS * fixP)2197 tc_gen_reloc (asection * section, fixS * fixP)
2198 {
2199 arelent * reloc;
2200 bfd_reloc_code_real_type code;
2201
2202 reloc = xmalloc (sizeof (* reloc));
2203
2204 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
2205 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
2206 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
2207
2208 if (fixP->fx_pcrel)
2209 {
2210 if (fixP->fx_r_type == BFD_RELOC_32)
2211 fixP->fx_r_type = BFD_RELOC_32_PCREL;
2212 else if (fixP->fx_r_type == BFD_RELOC_16)
2213 {
2214 fixP->fx_r_type = BFD_RELOC_16_PCREL;
2215 bfd_set_error (bfd_error_bad_value);
2216 }
2217 }
2218
2219 code = fixP->fx_r_type;
2220 if (pic_code)
2221 {
2222 #ifdef DEBUG_PIC
2223 printf("%s",bfd_get_reloc_code_name(code));
2224 #endif
2225 switch (code)
2226 {
2227 case BFD_RELOC_M32R_26_PCREL:
2228 code = BFD_RELOC_M32R_26_PLTREL;
2229 break;
2230
2231 case BFD_RELOC_M32R_24:
2232 if (fixP->fx_addsy != NULL
2233 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
2234 code = BFD_RELOC_M32R_GOTPC24;
2235 else
2236 code = BFD_RELOC_M32R_GOT24;
2237 break;
2238
2239 case BFD_RELOC_M32R_HI16_ULO:
2240 if (fixP->fx_addsy != NULL
2241 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
2242 code = BFD_RELOC_M32R_GOTPC_HI_ULO;
2243 else
2244 code = BFD_RELOC_M32R_GOT16_HI_ULO;
2245 break;
2246
2247 case BFD_RELOC_M32R_HI16_SLO:
2248 if (fixP->fx_addsy != NULL
2249 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
2250 code = BFD_RELOC_M32R_GOTPC_HI_SLO;
2251 else
2252 code = BFD_RELOC_M32R_GOT16_HI_SLO;
2253 break;
2254
2255 case BFD_RELOC_M32R_LO16:
2256 if (fixP->fx_addsy != NULL
2257 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
2258 code = BFD_RELOC_M32R_GOTPC_LO;
2259 else
2260 code = BFD_RELOC_M32R_GOT16_LO;
2261 break;
2262
2263 default:
2264 break;
2265 }
2266 #ifdef DEBUG_PIC
2267 printf(" => %s",bfd_get_reloc_code_name(code));
2268 #endif
2269 }
2270
2271 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2272
2273 #ifdef DEBUG_PIC
2274 printf(" => %s\n",reloc->howto->name);
2275 #endif
2276
2277 if (reloc->howto == (reloc_howto_type *) NULL)
2278 {
2279 as_bad_where (fixP->fx_file, fixP->fx_line,
2280 _("internal error: can't export reloc type %d (`%s')"),
2281 fixP->fx_r_type, bfd_get_reloc_code_name (code));
2282 return NULL;
2283 }
2284
2285 /* Use fx_offset for these cases. */
2286 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
2287 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2288 || fixP->fx_r_type == BFD_RELOC_32_PCREL)
2289 reloc->addend = fixP->fx_offset;
2290 else if ((!pic_code
2291 && code != BFD_RELOC_M32R_26_PLTREL)
2292 && fixP->fx_pcrel
2293 && fixP->fx_addsy != NULL
2294 && (S_GET_SEGMENT(fixP->fx_addsy) != section)
2295 && S_IS_DEFINED (fixP->fx_addsy)
2296 && ! S_IS_EXTERNAL(fixP->fx_addsy)
2297 && ! S_IS_WEAK(fixP->fx_addsy))
2298 /* Already used fx_offset in the opcode field itseld. */
2299 reloc->addend = fixP->fx_offset;
2300 else
2301 reloc->addend = fixP->fx_addnumber;
2302
2303 return reloc;
2304 }
2305
2306 inline static char *
m32r_end_of_match(char * cont,char * what)2307 m32r_end_of_match (char *cont, char *what)
2308 {
2309 int len = strlen (what);
2310
2311 if (strncasecmp (cont, what, strlen (what)) == 0
2312 && ! is_part_of_name (cont[len]))
2313 return cont + len;
2314
2315 return NULL;
2316 }
2317
2318 int
m32r_parse_name(char const * name,expressionS * exprP,enum expr_mode mode,char * nextcharP)2319 m32r_parse_name (char const *name,
2320 expressionS *exprP,
2321 enum expr_mode mode,
2322 char *nextcharP)
2323 {
2324 char *next = input_line_pointer;
2325 char *next_end;
2326 int reloc_type;
2327 operatorT op_type;
2328 segT segment;
2329
2330 exprP->X_op_symbol = NULL;
2331 exprP->X_md = BFD_RELOC_UNUSED;
2332
2333 if (strcmp (name, GOT_NAME) == 0)
2334 {
2335 if (! GOT_symbol)
2336 GOT_symbol = symbol_find_or_make (name);
2337
2338 exprP->X_add_symbol = GOT_symbol;
2339 no_suffix:
2340 /* If we have an absolute symbol or a
2341 reg, then we know its value now. */
2342 segment = S_GET_SEGMENT (exprP->X_add_symbol);
2343 if (mode != expr_defer && segment == absolute_section)
2344 {
2345 exprP->X_op = O_constant;
2346 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
2347 exprP->X_add_symbol = NULL;
2348 }
2349 else if (mode != expr_defer && segment == reg_section)
2350 {
2351 exprP->X_op = O_register;
2352 exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
2353 exprP->X_add_symbol = NULL;
2354 }
2355 else
2356 {
2357 exprP->X_op = O_symbol;
2358 exprP->X_add_number = 0;
2359 }
2360
2361 return 1;
2362 }
2363
2364 exprP->X_add_symbol = symbol_find_or_make (name);
2365
2366 if (*nextcharP != '@')
2367 goto no_suffix;
2368 else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF")))
2369 {
2370 reloc_type = BFD_RELOC_M32R_GOTOFF;
2371 op_type = O_PIC_reloc;
2372 }
2373 else if ((next_end = m32r_end_of_match (next + 1, "GOT")))
2374 {
2375 reloc_type = BFD_RELOC_M32R_GOT24;
2376 op_type = O_PIC_reloc;
2377 }
2378 else if ((next_end = m32r_end_of_match (next + 1, "PLT")))
2379 {
2380 reloc_type = BFD_RELOC_M32R_26_PLTREL;
2381 op_type = O_PIC_reloc;
2382 }
2383 else
2384 goto no_suffix;
2385
2386 *input_line_pointer = *nextcharP;
2387 input_line_pointer = next_end;
2388 *nextcharP = *input_line_pointer;
2389 *input_line_pointer = '\0';
2390
2391 exprP->X_op = op_type;
2392 exprP->X_add_number = 0;
2393 exprP->X_md = reloc_type;
2394
2395 return 1;
2396 }
2397
2398 int
m32r_cgen_parse_fix_exp(int opinfo,expressionS * exp)2399 m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp)
2400 {
2401 if (exp->X_op == O_PIC_reloc
2402 && exp->X_md == BFD_RELOC_M32R_26_PLTREL)
2403 {
2404 exp->X_op = O_symbol;
2405 opinfo = exp->X_md;
2406 }
2407
2408 return opinfo;
2409 }
2410