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Searched refs:op0 (Results 1 – 12 of 12) sorted by relevance

/toolchain/binutils/binutils-2.25/opcodes/
Dsparc-dis.c253 sparc_opcode *op0 = * (sparc_opcode **) a; in compare_opcodes() local
255 unsigned long int match0 = op0->match, match1 = op1->match; in compare_opcodes()
256 unsigned long int lose0 = op0->lose, lose1 = op1->lose; in compare_opcodes()
264 if (op0->architecture & current_arch_mask) in compare_opcodes()
273 else if (op0->architecture != op1->architecture) in compare_opcodes()
274 return op0->architecture - op1->architecture; in compare_opcodes()
285 op0->name, match0, lose0); in compare_opcodes()
286 op0->lose &= ~op0->match; in compare_opcodes()
287 lose0 = op0->lose; in compare_opcodes()
328 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); in compare_opcodes()
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Drl78-decode.opc172 int op0, op1;
449 op0 = SFR;
450 ID(mov); DM(None, op0); DB(bit); SC(0);
451 if (op0 == RL78_SFR_PSW && bit == 7)
749 op0 = SFR;
751 ID(mov); DM(None, op0); SC(op1);
752 if (op0 == 0xffffb)
1057 op0 = SFR;
1058 ID(mov); DM(None, op0); DB(bit); SC(1);
1059 if (op0 == RL78_SFR_PSW && bit == 7)
Drl78-decode.c173 int op0, op1; in rl78_decode_opcode() local
3649 op0 = SFR; in rl78_decode_opcode()
3650 ID(mov); DM(None, op0); DB(bit); SC(1); in rl78_decode_opcode()
3651 if (op0 == RL78_SFR_PSW && bit == 7) in rl78_decode_opcode()
3677 op0 = SFR; in rl78_decode_opcode()
3678 ID(mov); DM(None, op0); DB(bit); SC(0); in rl78_decode_opcode()
3679 if (op0 == RL78_SFR_PSW && bit == 7) in rl78_decode_opcode()
5154 op0 = SFR; in rl78_decode_opcode()
5156 ID(mov); DM(None, op0); SC(op1); in rl78_decode_opcode()
5157 if (op0 == 0xffffb) in rl78_decode_opcode()
Dbfin-dis.c2951 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); in decode_dsp32mac_0() local
2955 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) in decode_dsp32mac_0()
2983 if (w0 == 1 || op0 != 3) in decode_dsp32mac_0()
2991 if (w0 == 1 || op0 != 3) in decode_dsp32mac_0()
3000 if (op0 == 3) in decode_dsp32mac_0()
3006 decode_macfunc (0, op0, h00, h10, src0, src1, outf); in decode_dsp32mac_0()
Daarch64-opc.c2697 #define CPENC(op0,op1,crn,crm,op2) \ argument
2698 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
/toolchain/binutils/binutils-2.25/bfd/
Delf32-h8300.c1233 unsigned char op0, op1, op2, op3; in elf32_h8_relax_section() local
1284 op0 = bfd_get_8 (abfd, op_ptr + 0); in elf32_h8_relax_section()
1289 if (op0 == 0x01 in elf32_h8_relax_section()
1313 op0 = bfd_get_8 (abfd, op_ptr + 0); in elf32_h8_relax_section()
1316 if (op0 == 0x7a in elf32_h8_relax_section()
1377 unsigned char op0, op1, op2, op3, op0n, op1n; in elf32_h8_relax_section() local
1388 op0 = bfd_get_8 (abfd, contents + irel->r_offset - 4); in elf32_h8_relax_section()
1393 if (op0 == 0x78) in elf32_h8_relax_section()
Dxtensa-modules.c21270 int op0 = insn[0] & 0xf; in length_decoder() local
21271 return length_table[op0]; in length_decoder()
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-bfin.c1181 int h01, int h11, int h00, int h10, int op0, in bfin_gen_dsp32mac() argument
1186 ASSIGN (op0); in bfin_gen_dsp32mac()
1214 int h01, int h11, int h00, int h10, int op0, in bfin_gen_dsp32mult() argument
1219 ASSIGN (op0); in bfin_gen_dsp32mult()
2278 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); in decode_dsp32mac_0() local
2280 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) in decode_dsp32mac_0()
2303 if (w0 == 1 || op0 != 3) in decode_dsp32mac_0()
Dbfin-parse.y32 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \ argument
33 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
36 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \ argument
37 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
739 int op0, op1; variable
751 op0 = $1.op;
761 op0 = 3;
769 &$1.dst, op0, &$1.s0, &$1.s1, w0);
Dtc-aarch64.c3337 unsigned int op0, op1, cn, cm, op2; in parse_sys_reg() local
3339 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) in parse_sys_reg()
3342 if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7) in parse_sys_reg()
3344 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2; in parse_sys_reg()
Dtc-msp430.c166 int op0; /* Opcode for first word of short jump. */ member
3145 bfd_putl16 ((bfd_vma) hc.op0, frag); in msp430_operands()
/toolchain/binutils/binutils-2.25/gas/
DChangeLog477 * config/tc-aarch64.c (parse_sys_reg): Remove the restriction on op0