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/toolchain/binutils/binutils-2.25/include/opcode/
Dtic4x.h227 unsigned long opcode; member
309 #define A_CLASS_INSN(name, opcode, level) \ argument
310 { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
311 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
312 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
313 { name, opcode|0x00600000, 0xffe00000, "S,R", level }
322 #define AB_CLASS_INSN(name, opcode, level) \ argument
323 { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \
324 { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \
325 { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dmicromips.l2 .*:39: Error: opcode not supported in the `insn32' mode `nop16'
3 .*:98: Error: opcode not supported in the `insn32' mode `move16 \$2,\$22'
4 .*:99: Error: opcode not supported in the `insn32' mode `move16 \$22,\$2'
5 .*:106: Error: opcode not supported in the `insn32' mode `b16 test'
6 .*:111: Error: opcode not supported in the `insn32' mode `b16 1f'
7 .*:117: Error: opcode not supported in the `insn32' mode `b16 1b'
8 .*:277: Error: opcode not supported in the `insn32' mode `and16 \$2,\$2,\$3'
9 .*:315: Error: opcode not supported in the `insn32' mode `andi16 \$7,65535'
10 .*:387: Error: opcode not supported in the `insn32' mode `beqz16 \$16,test2'
11 .*:475: Error: opcode not supported in the `insn32' mode `bnez16 \$16,test3'
[all …]
Dr6-removed.l2 .*:3: Error: opcode not supported on this processor: .* \(.*\) `abs.ps \$f0,\$f2'
4 .*:5: Error: opcode not supported on this processor: .* \(.*\) `addi \$15,\$16,256'
6 .*:7: Error: opcode not supported on this processor: .* \(.*\) `bc0f 1f'
8 .*:9: Error: opcode not supported on this processor: .* \(.*\) `bc0t 1f'
10 .*:11: Error: opcode not supported on this processor: .* \(.*\) `bc1f 1f'
12 .*:13: Error: opcode not supported on this processor: .* \(.*\) `bc1t 1f'
14 .*:15: Error: opcode not supported on this processor: .* \(.*\) `bc2f 1f'
16 .*:17: Error: opcode not supported on this processor: .* \(.*\) `bc2t 1f'
18 .*:19: Error: opcode not supported on this processor: .* \(.*\) `bc3f 1f'
20 .*:21: Error: opcode not supported on this processor: .* \(.*\) `bc3t 1f'
[all …]
Dmips4-fp.l2 .*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label'
4 .*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
6 .*:8: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
8 .*:10: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
10 .*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
12 .*:15: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
14 .*:17: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
16 .*:19: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
18 .*:21: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
20 .*:23: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/
Drd-dw2-6.d8 \[0x.*\] Extended opcode 2: set Address to 0x0
9 \[0x.*\] Special opcode .*: advance Address by 0 to 0x0 and Line by 7 to 8
10 \[0x.*\] Special opcode .*: advance Address by 2 to 0x2 and Line by 2 to 10
12 \[0x.*\] Special opcode .*: advance Address by 0 to 0x7e6a and Line by 3 to 13
14 \[0x.*\] Special opcode .*: advance Address by 0 to 0x7f2e and Line by 6 to 19
15 \[0x.*\] Special opcode .*: advance Address by 2 to 0x7f30 and Line by 1 to 20
16 \[0x.*\] Special opcode .*: advance Address by 2 to 0x7f32 and Line by 1 to 21
17 \[0x.*\] Special opcode .*: advance Address by 2 to 0x7f34 and Line by 1 to 22
18 \[0x.*\] Special opcode .*: advance Address by 2 to 0x7f36 and Line by 1 to 23
19 \[0x.*\] Special opcode .*: advance Address by 2 to 0x7f38 and Line by 1 to 24
[all …]
Drd-dw2-15.d8 \[0x.*\] Extended opcode 2: set Address to 0x0
9 \[0x.*\] Special opcode .*: advance Address by 0 to 0x0 and Line by 8 to 9
10 \[0x.*\] Special opcode .*: advance Address by 2 to 0x2 and Line by 1 to 10
11 \[0x.*\] Special opcode .*: advance Address by 2 to 0x4 and Line by 2 to 12
12 \[0x.*\] Special opcode .*: advance Address by 2 to 0x6 and Line by 1 to 13
13 \[0x.*\] Special opcode .*: advance Address by 2 to 0x8 and Line by 2 to 15
14 \[0x.*\] Special opcode .*: advance Address by 2 to 0xa and Line by 1 to 16
15 \[0x.*\] Special opcode .*: advance Address by 2 to 0xc and Line by 2 to 18
16 \[0x.*\] Special opcode .*: advance Address by 2 to 0xe and Line by 1 to 19
17 \[0x.*\] Special opcode .*: advance Address by 2 to 0x10 and Line by 2 to 21
[all …]
Drd-dw2-12.d8 \[0x.*\] Extended opcode 2: set Address to 0x0
9 \[0x.*\] Special opcode .*: advance Address by 0 to 0x0 and Line by 4 to 5
10 \[0x.*\] Special opcode .*: advance Address by 4 to 0x4 and Line by 1 to 6
11 \[0x.*\] Special opcode .*: advance Address by 4 to 0x8 and Line by 1 to 7
12 \[0x.*\] Special opcode .*: advance Address by 4 to 0xc and Line by 2 to 9
13 \[0x.*\] Special opcode .*: advance Address by 4 to 0x10 and Line by 1 to 10
14 \[0x.*\] Special opcode .*: advance Address by 4 to 0x14 and Line by 1 to 11
15 \[0x.*\] Special opcode .*: advance Address by 4 to 0x18 and Line by 2 to 13
16 \[0x.*\] Special opcode .*: advance Address by 4 to 0x1c and Line by 1 to 14
17 \[0x.*\] Special opcode .*: advance Address by 4 to 0x20 and Line by 1 to 15
[all …]
Drd-dw2-9.d8 \[0x.*\] Extended opcode 2: set Address to 0x0
9 \[0x.*\] Special opcode .*: advance Address by 0 to 0x0 and Line by 3 to 4
10 \[0x.*\] Special opcode .*: advance Address by 2 to 0x2 and Line by 4 to 8
11 \[0x.*\] Special opcode .*: advance Address by 4 to 0x6 and Line by 1 to 9
12 \[0x.*\] Special opcode .*: advance Address by 4 to 0xa and Line by 1 to 10
20 \[0x.*\] Special opcode .*: advance Address by 0 to 0x8178 and Line by 4 to 71
21 \[0x.*\] Special opcode .*: advance Address by 2 to 0x817a and Line by 1 to 72
22 \[0x.*\] Special opcode .*: advance Address by 2 to 0x817c and Line by 1 to 73
23 \[0x.*\] Special opcode .*: advance Address by 2 to 0x817e and Line by 1 to 74
24 \[0x.*\] Special opcode .*: advance Address by 2 to 0x8180 and Line by 1 to 75
[all …]
Drd-dw2-13.d8 \[0x.*\] Extended opcode 2: set Address to 0x0
9 \[0x.*\] Special opcode .*: advance Address by 0 to 0x0 and Line by 5 to 6
10 \[0x.*\] Special opcode .*: advance Address by 6 to 0x6 and Line by 1 to 7
11 \[0x.*\] Special opcode .*: advance Address by 8 to 0xe and Line by 1 to 8
12 \[0x.*\] Special opcode .*: advance Address by 6 to 0x14 and Line by 1 to 9
13 \[0x.*\] Special opcode .*: advance Address by 6 to 0x1a and Line by 1 to 10
14 \[0x.*\] Special opcode .*: advance Address by 6 to 0x20 and Line by 1 to 11
15 \[0x.*\] Special opcode .*: advance Address by 8 to 0x28 and Line by 1 to 12
16 \[0x.*\] Special opcode .*: advance Address by 6 to 0x2e and Line by 1 to 13
17 \[0x.*\] Special opcode .*: advance Address by 4 to 0x32 and Line by 3 to 16
[all …]
Drd-dw2-2.d8 \[0x.*\] Extended opcode 2: set Address to 0x5005a
11 \[0x.*\] Special opcode .*: advance Address by 4 to 0x5005e and Line by 1 to 38
12 \[0x.*\] Special opcode .*: advance Address by 4 to 0x50062 and Line by 1 to 39
13 \[0x.*\] Special opcode .*: advance Address by 4 to 0x50066 and Line by 1 to 40
14 \[0x.*\] Special opcode .*: advance Address by 4 to 0x5006a and Line by 2 to 42
15 \[0x.*\] Special opcode .*: advance Address by 4 to 0x5006e and Line by 1 to 43
16 \[0x.*\] Special opcode .*: advance Address by 4 to 0x50072 and Line by 1 to 44
17 \[0x.*\] Special opcode .*: advance Address by 4 to 0x50076 and Line by 1 to 45
18 \[0x.*\] Special opcode .*: advance Address by 4 to 0x5007a and Line by 2 to 47
19 \[0x.*\] Special opcode .*: advance Address by 4 to 0x5007e and Line by 1 to 48
[all …]
Drd-dw2-14.d8 \[0x.*\] Extended opcode 2: set Address to 0x0
9 \[0x.*\] Special opcode .*: advance Address by 0 to 0x0 and Line by 8 to 9
10 \[0x.*\] Special opcode .*: advance Address by 2 to 0x2 and Line by 1 to 10
11 \[0x.*\] Special opcode .*: advance Address by 4 to 0x6 and Line by 1 to 11
12 \[0x.*\] Special opcode .*: advance Address by 4 to 0xa and Line by 1 to 12
13 \[0x.*\] Special opcode .*: advance Address by 8 to 0x12 and Line by 1 to 13
14 \[0x.*\] Special opcode .*: advance Address by 8 to 0x1a and Line by 1 to 14
15 \[0x.*\] Special opcode .*: advance Address by 2 to 0x1c and Line by 1 to 15
16 \[0x.*\] Special opcode .*: advance Address by 4 to 0x20 and Line by 1 to 16
17 \[0x.*\] Special opcode .*: advance Address by 4 to 0x24 and Line by 1 to 17
[all …]
Drd-dw2-11.d8 \[0x.*\] Extended opcode 2: set Address to 0x0
9 \[0x.*\] Special opcode .*: advance Address by 0 to 0x0 and Line by 4 to 5
10 \[0x.*\] Special opcode .*: advance Address by 2 to 0x2 and Line by 1 to 6
12 \[0x.*\] Special opcode .*: advance Address by 0 to 0x80 and Line by 2 to 8
13 \[0x.*\] Special opcode .*: advance Address by 2 to 0x82 and Line by 1 to 9
15 \[0x.*\] Special opcode .*: advance Address by 0 to 0x164 and Line by 6 to 15
16 \[0x.*\] Special opcode .*: advance Address by 4 to 0x168 and Line by 1 to 16
18 \[0x.*\] Special opcode .*: advance Address by 0 to 0x1e6 and Line by 2 to 18
19 \[0x.*\] Special opcode .*: advance Address by 4 to 0x1ea and Line by 1 to 19
21 \[0x.*\] Special opcode .*: advance Address by 0 to 0x650 and Line by 6 to 25
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/
Dmovpc.l2 .*:6: Error: Invalid opcode/operands
3 .*:7: Error: Unrecognized opcode: .*
4 .*:7: Error: Invalid opcode/operands
5 .*:8: Error: Unrecognized opcode: .*
6 .*:8: Error: Invalid opcode/operands
7 .*:9: Error: Unrecognized opcode: .*
8 .*:9: Error: Invalid opcode/operands
9 .*:10: Error: Unrecognized opcode: .*
10 .*:10: Error: Invalid opcode/operands
11 .*:11: Error: Unrecognized opcode: .*
[all …]
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-mn10200.c346 int opcode = fragP->fr_literal[offset] & 0xff; in md_convert_frag() local
348 switch (opcode) in md_convert_frag()
351 opcode = 0xe9; in md_convert_frag()
354 opcode = 0xe8; in md_convert_frag()
357 opcode = 0xe2; in md_convert_frag()
360 opcode = 0xe0; in md_convert_frag()
363 opcode = 0xe1; in md_convert_frag()
366 opcode = 0xe3; in md_convert_frag()
369 opcode = 0xe6; in md_convert_frag()
372 opcode = 0xe4; in md_convert_frag()
[all …]
Dtc-tic30.c245 unsigned opcode; member
259 insn_template *opcode; variable
264 unsigned opcode; /* Final opcode. */ member
584 current_op->reg.opcode = regop->opcode; in tic30_operand()
650 unsigned opcode; /* Final opcode. */ member
923 if ((p_insn.operand_type[0][2]->reg.opcode != 0x00) in tic30_parallel_insn()
924 && (p_insn.operand_type[0][2]->reg.opcode != 0x01)) in tic30_parallel_insn()
930 if ((p_insn.operand_type[1][2]->reg.opcode != 0x02) in tic30_parallel_insn()
931 && (p_insn.operand_type[1][2]->reg.opcode != 0x03)) in tic30_parallel_insn()
979 p_insn.opcode = p_insn.tm->base_opcode; in tic30_parallel_insn()
[all …]
Dtc-mn10300.c484 int opcode = fragP->fr_literal[offset] & 0xff; in md_convert_frag() local
486 switch (opcode) in md_convert_frag()
489 opcode = 0xc9; in md_convert_frag()
492 opcode = 0xc8; in md_convert_frag()
495 opcode = 0xc2; in md_convert_frag()
498 opcode = 0xc0; in md_convert_frag()
501 opcode = 0xc1; in md_convert_frag()
504 opcode = 0xc3; in md_convert_frag()
507 opcode = 0xc6; in md_convert_frag()
510 opcode = 0xc4; in md_convert_frag()
[all …]
Dtc-moxie.c64 const moxie_opc_info_t *opcode; in md_begin() local
68 for (count = 0, opcode = moxie_form1_opc_info; count++ < 64; opcode++) in md_begin()
69 hash_insert (opcode_hash_control, opcode->name, (char *) opcode); in md_begin()
71 for (count = 0, opcode = moxie_form2_opc_info; count++ < 4; opcode++) in md_begin()
72 hash_insert (opcode_hash_control, opcode->name, (char *) opcode); in md_begin()
74 for (count = 0, opcode = moxie_form3_opc_info; count++ < 10; opcode++) in md_begin()
75 hash_insert (opcode_hash_control, opcode->name, (char *) opcode); in md_begin()
159 moxie_opc_info_t *opcode; in md_assemble() local
183 opcode = (moxie_opc_info_t *) hash_find (opcode_hash_control, op_start); in md_assemble()
186 if (opcode == NULL) in md_assemble()
[all …]
Dtc-m68hc11.c159 struct m68hc11_opcode *opcode; member
186 struct m9s12xg_opcode *opcode; member
486 opc->opcode->name, in m68hc11_print_statistics()
668 opc->opcode = opcodes; in md_begin()
735 print_opcode_format (struct m68hc11_opcode *opcode, int example) in print_opcode_format() argument
738 int format = opcode->format; in print_opcode_format()
1013 struct m68hc11_opcode *opcode; in print_insn_format() local
1022 opcode = opc->opcode; in print_insn_format()
1029 fmt = print_opcode_format (opcode, 0); in print_insn_format()
1030 sprintf (buf, "\t%-5.5s %s", opcode->name, fmt); in print_insn_format()
[all …]
/toolchain/binutils/binutils-2.25/opcodes/
Dtic54x-dis.c52 unsigned short opcode; in print_insn_tic54x() local
63 opcode = bfd_getl16 (opbuf); in print_insn_tic54x()
64 tm = tic54x_get_insn (info, memaddr, opcode, &size); in print_insn_tic54x()
73 if (!print_parallel_instruction (info, memaddr, opcode, tm, size)) in print_insn_tic54x()
78 if (!print_instruction (info, memaddr, opcode, in print_insn_tic54x()
110 if (tm->opcode == (memdata & tm->mask)) in tic54x_get_insn()
140 if (tm->opcode == (memdata & tm->mask)) in tic54x_get_insn()
172 unsigned short opcode, in print_instruction() argument
214 sprint_dual_address (info, operand[i], XMEM (opcode)); in print_instruction()
218 sprint_dual_address (info, operand[i], YMEM (opcode)); in print_instruction()
[all …]
Dnios2-dis.c44 const struct nios2_opcode *opcode; member
119 new_hash->opcode = op; in nios2_init_opcode_hash()
135 printf ("%s ", tmp_hash->opcode->name); in nios2_init_opcode_hash()
147 printf ("%s ", tmp_hash->opcode->name); in nios2_init_opcode_hash()
158 nios2_find_opcode_hash (unsigned long opcode, in nios2_find_opcode_hash() argument
172 if (state->nop->match == (opcode & state->nop->mask)) in nios2_find_opcode_hash()
176 for (entry = state->ps_hash[state->extract_opcode (opcode)]; in nios2_find_opcode_hash()
178 if (entry->opcode->match == (opcode & entry->opcode->mask)) in nios2_find_opcode_hash()
179 return entry->opcode; in nios2_find_opcode_hash()
182 for (entry = state->hash[state->extract_opcode (opcode)]; in nios2_find_opcode_hash()
[all …]
Ds390-dis.c46 opc_index[s390_opcodes[i].opcode[0]] = i; in init_disasm()
82 const struct s390_opcode *opcode) in s390_insn_matches_opcode() argument
84 return (buffer[1] & opcode->mask[1]) == opcode->opcode[1] in s390_insn_matches_opcode()
85 && (buffer[2] & opcode->mask[2]) == opcode->opcode[2] in s390_insn_matches_opcode()
86 && (buffer[3] & opcode->mask[3]) == opcode->opcode[3] in s390_insn_matches_opcode()
87 && (buffer[4] & opcode->mask[4]) == opcode->opcode[4] in s390_insn_matches_opcode()
88 && (buffer[5] & opcode->mask[5]) == opcode->opcode[5]; in s390_insn_matches_opcode()
156 const struct s390_opcode *opcode) in s390_print_insn_with_opcode() argument
162 info->fprintf_func (info->stream, "%s", opcode->name); in s390_print_insn_with_opcode()
166 for (opindex = opcode->operands; *opindex != 0; opindex++) in s390_print_insn_with_opcode()
[all …]
Dalpha-dis.c63 const struct alpha_opcode *opcode, *opcode_end; local
71 opcode = alpha_opcodes;
72 opcode_end = opcode + alpha_num_opcodes;
76 opcode_index[op] = opcode;
77 while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
78 ++opcode;
80 opcode_index[op] = opcode;
119 for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
121 if ((insn ^ opcode->opcode) & opcode->mask)
124 if (!(opcode->flags & isa_mask))
[all …]
Di370-dis.c37 const struct i370_opcode *opcode; in print_insn_i370() local
58 for (opcode = i370_opcodes; opcode < opcode_end; opcode++) in print_insn_i370()
67 if (2 == opcode->len) in print_insn_i370()
72 masked.i[0] &= opcode->mask.i[0]; in print_insn_i370()
73 if (masked.i[0] != opcode->opcode.i[0]) in print_insn_i370()
76 if (6 == opcode->len) in print_insn_i370()
78 masked.i[1] &= opcode->mask.i[1]; in print_insn_i370()
79 if (masked.i[1] != opcode->opcode.i[1]) in print_insn_i370()
84 if (2 == opcode->len) in print_insn_i370()
94 for (opindex = opcode->operands; *opindex != 0; opindex++) in print_insn_i370()
[all …]
Dmoxie-dis.c48 const moxie_opc_info_t * opcode; in print_insn_moxie() local
65 opcode = &moxie_form1_opc_info[iword >> 8]; in print_insn_moxie()
66 switch (opcode->itype) in print_insn_moxie()
69 fpr (stream, "%s", opcode->name); in print_insn_moxie()
72 fpr (stream, "%s\t%s", opcode->name, in print_insn_moxie()
76 fpr (stream, "%s\t%s, %s", opcode->name, in print_insn_moxie()
89 fpr (stream, "%s\t%s, 0x%x", opcode->name, in print_insn_moxie()
103 fpr (stream, "%s\t0x%x", opcode->name, imm); in print_insn_moxie()
116 fpr (stream, "%s\t", opcode->name); in print_insn_moxie()
122 fpr (stream, "%s\t(%s), %s", opcode->name, in print_insn_moxie()
[all …]
Daarch64-asm.c78 insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask); in aarch64_ins_reglane()
80 if (inst->opcode->iclass == asisdone || inst->opcode->iclass == asimdins) in aarch64_ins_reglane()
84 && inst->opcode->operands[0] == AARCH64_OPND_Ed) in aarch64_ins_reglane()
151 unsigned num = get_opcode_dependent_value (inst->opcode); in aarch64_ins_ldst_reglist()
195 int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1; in aarch64_ins_ldst_reglist_r()
269 if (inst->opcode->iclass == asimdshf) in aarch64_ins_advsimd_imm_shift()
283 insert_field (FLD_Q, code, Q, inst->opcode->mask); in aarch64_ins_advsimd_imm_shift()
441 if (inst->opcode->op == OP_BIC) in aarch64_ins_limm()
464 if (inst->opcode->iclass == ldstpair_indexed in aarch64_ins_ft()
465 || inst->opcode->iclass == ldstnapair_offs in aarch64_ins_ft()
[all …]

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