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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dexpected_comparison_errors.l2 .*:1: Error: AREGs are in bad order or same. Input text was A0.
3 .*:2: Error: AREGs are in bad order or same. Input text was A1.
4 .*:3: Error: AREGs are in bad order or same. Input text was A0.
5 .*:4: Error: AREGs are in bad order or same. Input text was a0.
6 .*:5: Error: AREGs are in bad order or same. Input text was a1.
7 .*:6: Error: AREGs are in bad order or same. Input text was a0.
8 .*:7: Error: AREGs are in bad order or same. Input text was a0.
9 .*:8: Error: AREGs are in bad order or same. Input text was a1.
10 .*:9: Error: AREGs are in bad order or same. Input text was a0.
/toolchain/binutils/binutils-2.25/ld/
Dmri.c49 static struct section_name_struct *order; variable
134 if (order == NULL) in mri_draw_tree()
135 order = address; in mri_draw_tree()
143 for (olist = order; done == 0 && olist != NULL; olist = olist->next) in mri_draw_tree()
155 mri_add_to_list (&order, alist->name, alist->vma, 0, 0, 0); in mri_draw_tree()
167 if (order == NULL) in mri_draw_tree()
168 order = only_load; in mri_draw_tree()
172 for (ptr2 = order; ptr2; ptr2 = ptr2->next) in mri_draw_tree()
181 for (ptr = order; ptr; ptr = ptr->next) in mri_draw_tree()
186 if (order != NULL) in mri_draw_tree()
[all …]
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/
Dtls-hidden4.got6 # The order of the TLS entries in this GOT is:
13 # The order and address don't matter; the important thing is that the
21 # Likewise, but the order of the entries in this GOT is:
Dtls-hidden3.got12 # The order of the TLS entries is:
19 # Any order would be acceptable, but it must match the .d dump.
Deh-frame5.d6 # The order of the relocations doesn't really matter, but they must
Dpic-and-nonpic-4b.nd3 # The order of the next two symbols is not important.
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/
Dccr.s36 ; Two from same group, and switch order.
45 ; Two from different groups, and switch order.
50 ; Four in same group, and switch order.
59 ; Four in different groups, and switch order.
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/
Dbittest.l2 .*: Warning: Swapping instruction order
6 .*: Warning: Swapping instruction order
22 .* Warning: Swapping instruction order
40 .* Warning: Swapping instruction order
Dmul.s5 # in IU in consecutive cycles in the order (a)->(b). It does neither prohibit
6 # executions in the reverse order (b)-> (a) nor consecutive execution of
/toolchain/binutils/binutils-2.25/gold/
Dcommon.cc156 const char* order = parameters->options().sort_common(); in allocate_commons() local
157 if (*order == '\0' || strcmp(order, "descending") == 0) in allocate_commons()
159 else if (strcmp(order, "ascending") == 0) in allocate_commons()
163 gold_error("invalid --sort-common argument: %s", order); in allocate_commons()
/toolchain/binutils/binutils-2.25/opcodes/
Dd10v-dis.c196 int order) in dis_2_short() argument
239 switch (order) in dis_2_short()
243 order = -1; in dis_2_short()
247 order = -1; in dis_2_short()
251 order = -1; in dis_2_short()
Dcgen-ibld.in233 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
235 recorded in host byte order, otherwise BUFFER is an array of bytes
236 and the value is recorded in target byte order).
254 target byte order handling is deferred until later. */
395 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
498 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
Dia64-gen.c133 int order; member
1735 add_dis_table_ent (struct disent *which, int insn, int order, in add_dis_table_ent() argument
1761 ent->priority = order; in add_dis_table_ent()
1788 ia64_insn mask, int opcodenum, int order, in insert_bit_table_ent() argument
1798 opcodenum, order, in insert_bit_table_ent()
1817 insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum, order, in insert_bit_table_ent()
1837 opcodenum, opcode_count - ent->order - 1, in add_dis_entry()
2232 || ent1->order != ent2->order) in completer_entries_eq()
2515 int order) in insert_completer_entry() argument
2582 (*ptr)->order = order; in insert_completer_entry()
/toolchain/binutils/binutils-2.25/libiberty/
Dfloatformat.c424 get_field (const unsigned char *data, enum floatformat_byteorders order, in get_field() argument
430 int nextbyte = (order == floatformat_little) ? 1 : -1; in get_field()
436 if (order == floatformat_little) in get_field()
562 put_field (unsigned char *data, enum floatformat_byteorders order, in put_field() argument
568 int nextbyte = (order == floatformat_little) ? 1 : -1; in put_field()
574 if (order == floatformat_little) in put_field()
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mt/
Dbadorder.s1 ; Good operands in the wrong order should generate an error.
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/
Dexpr-1.s2 % the known expression evaluation order mismatch problem.
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dattr-order.s2 @ are emitted in the proper order.
Dattr-order.d2 # source: attr-order.s
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-ia64/
Dlink-order.d1 #source: ../../../binutils/testsuite/binutils-all/link-order.s
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-elf/
Dorphan2.d5 # xstormy uses a non-standard script, resulting is unexpected section order
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/macros/
Dtest2.d3 # darwin(mach-o) reverses the order of relocs.
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-ia64.texi63 These options select the byte order. The @code{-mle} option selects little-endian
64 byte order (default) and @code{-mbe} selects big-endian byte order. Note that
65 IA-64 machine code always uses little-endian byte order.
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Delf-rel13.d11 # The next two lines could be in either order.
Delf-rel13-mips16.d11 # The next two lines could be in either order.
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-mmix/
Dloc3.d6 # Two text files in opposite order.

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