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Searched refs:powerpc_opcodes (Results 1 – 20 of 20) sorted by relevance

/toolchain/binutils/binutils-2.25/opcodes/
DChangeLog-2004215 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
386 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
396 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
489 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
542 (powerpc_opcodes): Use RA0 as appropriate.
546 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
639 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
643 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
647 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
651 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
[all …]
DChangeLog-2012122 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
131 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
175 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
274 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
280 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
373 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
395 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
568 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
823 (powerpc_opcodes): Add new VLE instructions. Update existing
926 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
Dppc-dis.c347 unsigned op = PPC_OP (powerpc_opcodes[i].opcode); in disassemble_init_powerpc()
472 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; in lookup_powerpc()
473 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; in lookup_powerpc()
DChangeLog-2010323 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
460 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
498 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
558 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
598 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
603 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
757 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
DChangeLog-2009636 (powerpc_opcodes): Update mnemonics where required for 476.
662 * ppc-opc.c (powerpc_opcodes): Remove support for the the "lxsdux",
701 * ppc-opc.c (powerpc_opcodes): Add eratilx, eratsx, eratsx.,
1362 * ppc-opc.c (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva",
1374 * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
1381 * ppc-opc.c (powerpc_opcodes) <"dcbzl">: Merge the POWER4 and
1430 * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
1468 (powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr",
1532 * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first
1563 (powerpc_opcodes) <"dcbt", "dcbtst">: Deprecate the Embedded operand
[all …]
DChangeLog-2008136 (powerpc_opcodes): Remove all BOOKE64 instructions.
338 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
367 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
385 (powerpc_opcodes): Add Xilinx APU related opcodes.
419 (powerpc_opcodes): Add mfdcrux and mtdcrux.
593 (powerpc_opcodes): Add new Power E500MC instructions.
847 * ppc-opc.c (powerpc_opcodes): Order and format.
DChangeLog-2007109 * ppc-opc.c (powerpc_opcodes): Remove the dcffix and dcffix. opcodes
208 * ppc-opc.c (powerpc_opcodes): Fix the first two operands of
214 (powerpc_opcodes): Sort psq_st and psq_stu according to major
1065 (powerpc_opcodes): Add all pair singles instructions.
1129 (powerpc_opcodes): Use it in dcba.
1476 (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
1497 (powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
1503 (powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand.
1518 * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc,
1523 * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe.
DChangeLog-2005129 * ppc-opc.c (powerpc_opcodes): Add frin,friz,frip,frim. Correct
453 (powerpc_opcodes): Mark icbt as available for the e300.
754 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
845 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
980 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
990 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
1201 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
DChangeLog-201113 (powerpc_opcodes): Use ISA_V2 to enable branch insns rather than
84 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
145 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
575 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
DChangeLog-000194 (powerpc_opcodes): Modify existing 32 bit insns with branch hints
226 (powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr,
483 (powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev",
855 * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of
1504 (powerpc_opcodes): Add table entries for PPC 405 instructions.
1549 * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd.
1663 * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
1827 * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
1853 (powerpc_opcodes): Add table entries for vector instructions.
DChangeLog-0203204 * ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries.
223 (powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci,
450 (powerpc_opcodes): Add Power4 version of "mfcr". Simplify "mtcr" mask.
535 (powerpc_opcodes): Add "attn", "lq" and "stq".
691 * ppc-opc.c (powerpc_opcodes): Readd tlbre for PPC403.
988 (powerpc_opcodes): Change PMRN to SPR.
1809 (powerpc_opcodes): Replace occurences of PPCCOM32 with NOPOWER4,
DChangeLog-92971400 (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
1983 (powerpc_opcodes): Add 860/821 specific SPRs.
2224 * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different
2791 * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci,
2827 (powerpc_opcodes): Add instructions to access special registers by
3035 * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and
3053 (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and
3058 * ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn
3075 (powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT.
3093 (powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and
[all …]
DChangeLog-2006146 (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
189 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
DChangeLog-2013870 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
980 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
DChangeLog117 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
DChangeLog-9899724 * ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions.
901 * ppc-opc.c (powerpc_opcodes): Add support for PowerPC 750 move
Dppc-opc.c2780 const struct powerpc_opcode powerpc_opcodes[] = { variable
6422 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
/toolchain/binutils/binutils-2.25/include/opcode/
Dppc.h65 extern const struct powerpc_opcode powerpc_opcodes[];
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-ppc.c1535 op_end = powerpc_opcodes + powerpc_num_opcodes; in ppc_setup_opcodes()
1536 for (op = powerpc_opcodes; op < op_end; op++) in ppc_setup_opcodes()
1540 if (op != powerpc_opcodes) in ppc_setup_opcodes()
1547 op->name, (unsigned int) (op - powerpc_opcodes), in ppc_setup_opcodes()
1581 for (op = powerpc_opcodes; op < op_end; op++) in ppc_setup_opcodes()
1600 op->name, (unsigned int) (op - powerpc_opcodes), in ppc_setup_opcodes()
/toolchain/binutils/binutils-2.25/gas/
DChangeLog-20081439 for strict ordering of powerpc_opcodes, but disable for now.