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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dthumb2_bad_reg.s8 adc r13, r0, #1
9 adc r15, r0, #1
10 adc r0, r13, #1
11 adc r0, r15, #1
13 adc.w r13, r0, r1
14 adc.w r15, r0, r1
15 adc.w r0, r13, r1
16 adc.w r0, r15, r1
17 adc.w r0, r1, r13
18 adc.w r0, r1, r15
[all …]
Darmv1.s4 and r0, r0, r0
5 ands r0, r0, r0
6 eor r0, r0, r0
7 eors r0, r0, r0
8 sub r0, r0, r0
9 subs r0, r0, r0
10 rsb r0, r0, r0
11 rsbs r0, r0, r0
12 add r0, r0, r0
13 adds r0, r0, r0
[all …]
Darch7em.s8 pkhbt r0, r0, r0
9 pkhbt r9, r0, r0
10 pkhbt r0, r9, r0
11 pkhbt r0, r0, r9
12 pkhbt r0, r0, r0, lsl #0x14
13 pkhbt r0, r0, r0, lsl #3
73 smlabb r0, r0, r0, r0
74 smlabb r9, r0, r0, r0
75 smlabb r0, r9, r0, r0
76 smlabb r0, r0, r9, r0
[all …]
Darmv1.d11 0+00 <[^>]*> e0000000 ? and r0, r0, r0
12 0+04 <[^>]*> e0100000 ? ands r0, r0, r0
13 0+08 <[^>]*> e0200000 ? eor r0, r0, r0
14 0+0c <[^>]*> e0300000 ? eors r0, r0, r0
15 0+10 <[^>]*> e0400000 ? sub r0, r0, r0
16 0+14 <[^>]*> e0500000 ? subs r0, r0, r0
17 0+18 <[^>]*> e0600000 ? rsb r0, r0, r0
18 0+1c <[^>]*> e0700000 ? rsbs r0, r0, r0
19 0+20 <[^>]*> e0800000 ? add r0, r0, r0
20 0+24 <[^>]*> e0900000 ? adds r0, r0, r0
[all …]
Dthumb32.s6 orr r0, r1, #0x00000000
7 orr r0, r1, #0x000000a5
8 orr r0, r1, #0x00a500a5
9 orr r0, r1, #0xa500a500
10 orr r0, r1, #0xa5a5a5a5
12 orr r0, r1, #0xa5 << 31
13 orr r0, r1, #0xa5 << 30
14 orr r0, r1, #0xa5 << 29
15 orr r0, r1, #0xa5 << 28
16 orr r0, r1, #0xa5 << 27
[all …]
Dgroup-reloc-ldrs.d8 0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
10 0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
12 0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
14 0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
16 0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
18 0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
20 0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
22 0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
24 0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
26 0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
[all …]
Dgroup-reloc-ldr.d8 0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
10 0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
12 0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
14 0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
16 0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
18 0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
20 0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
22 0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
24 0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
26 0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
[all …]
Dgroup-reloc-alu.d8 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
10 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
12 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
14 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
16 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
18 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
20 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
22 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
24 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
26 0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
[all …]
Darchv6t2.s3 bfi r0, r0, #0, #1
4 bfine r0, r0, #0, #1
6 bfi r9, r0, #0, #1
7 bfi r0, r9, #0, #1
8 bfi r0, r0, #0, #18
9 bfi r0, r0, #17, #1
11 bfi r0, #0, #0, #1
12 bfc r0, #0, #1
13 bfcne r0, #0, #1
15 bfc r0, #0, #18
[all …]
Dthumb2_bad_reg.l2 [^:]*:[0-9]+: Error: r13 not allowed here -- `adc r13,r0,#1'
4 [^:]*:[0-9]+: Error: r13 not allowed here -- `adc r0,r13,#1'
6 [^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r13,r0,r1'
8 [^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r0,r13,r1'
10 [^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r0,r1,r13'
12 [^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r13,r0,#1'
14 [^:]*:[0-9]+: Error: r13 not allowed here -- `addw r13,r0,#1'
16 [^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r13,r0,r1'
18 [^:]*:[0-9]+: Error: r15 not allowed here -- `adds.w r15,r0,r1'
20 [^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r0,r1,r13'
[all …]
Darmv8-a-bad.s7 swp r0, r1, [r2]
10 mcr p15, 0, r0, c7, c5, 4
14 mrc p14, 6, r0, c1, c0, 0
35 stlb pc, [r0]
36 stlb r0, [pc]
37 stlh pc, [r0]
38 stlh r0, [pc]
39 stl pc, [r0]
40 stl r0, [pc]
41 stlexb r1, pc, [r0]
[all …]
Darch7em.d9 0[0-9a-f]+ <[^>]+> eac0 0000 pkhbt r0, r0, r0
10 0[0-9a-f]+ <[^>]+> eac0 0900 pkhbt r9, r0, r0
11 0[0-9a-f]+ <[^>]+> eac9 0000 pkhbt r0, r9, r0
12 0[0-9a-f]+ <[^>]+> eac0 0009 pkhbt r0, r0, r9
13 0[0-9a-f]+ <[^>]+> eac0 5000 pkhbt r0, r0, r0, lsl #20
14 0[0-9a-f]+ <[^>]+> eac0 00c0 pkhbt r0, r0, r0, lsl #3
70 0[0-9a-f]+ <[^>]+> fb10 0000 smlabb r0, r0, r0, r0
71 0[0-9a-f]+ <[^>]+> fb10 0900 smlabb r9, r0, r0, r0
72 0[0-9a-f]+ <[^>]+> fb19 0000 smlabb r0, r9, r0, r0
73 0[0-9a-f]+ <[^>]+> fb10 0009 smlabb r0, r0, r9, r0
[all …]
Dsp-pc-validations-bad-t.s7 moveq r0, r0
13 moveq r0, r0
27 LOAD [r0]
28 LOAD [r0,#0]
31 LOADw [r0]
32 LOADw [r0,#0]
33 LOAD [r0,#-4]
34 LOAD [r0],#4
35 LOAD [r0,#0]!
43 LOAD [r0, r1]
[all …]
Darchv6t2.d8 0+00 <[^>]+> e7c00010 bfi r0, r0, #0, #1
9 0+04 <[^>]+> 17c00010 bfine r0, r0, #0, #1
10 0+08 <[^>]+> e7c09010 bfi r9, r0, #0, #1
11 0+0c <[^>]+> e7c00019 bfi r0, r9, #0, #1
12 0+10 <[^>]+> e7d10010 bfi r0, r0, #0, #18
13 0+14 <[^>]+> e7d10890 bfi r0, r0, #17, #1
14 0+18 <[^>]+> e7c0001f bfc r0, #0, #1
15 0+1c <[^>]+> e7c0001f bfc r0, #0, #1
16 0+20 <[^>]+> 17c0001f bfcne r0, #0, #1
18 0+28 <[^>]+> e7d1001f bfc r0, #0, #18
[all …]
Dsp-pc-validations-bad.s11 ldr r0,[r1,pc, LSL #2] @ Unpredictable
12 ldr r0,[r1,pc, LSL #2]! @ ditto
13 ldr r0,[r1],pc, LSL #2 @ ditto
14 ldr r0,[pc,r1, LSL #2]! @ ditto
15 ldr r0,[pc],r1, LSL #2 @ ditto
18 ldrb pc,[r0,#4] @ Unpredictable
19 ldrb pc,[r0],#4 @ ditto
20 ldrb pc,[r0,#4]! @ ditto
27 ldrb pc,[r0,r1, LSL #2] @ Unpredictable
28 ldrb pc,[r0,r1, LSL #2]! @ ditto
[all …]
Dthumb2_it.s7 addeq r0, r0, r2
8 addeq r0, r0, r8
9 addne r0, r1, r2
10 addseq r0, r1, r2
11 add r0, r0, r2
12 add r0, r0, r8
13 adds r0, r0, r2
14 adds r0, r0, r8
15 adds r0, r1, r2
18 orreq r0, r0, r2
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/m32r/
Doutofrange.s14 ld24 r0,#0
15 ld24 r0,#0
16 ld24 r0,#0
17 ld24 r0,#0
18 ld24 r0,#0
19 ld24 r0,#0
20 ld24 r0,#0
21 ld24 r0,#0
22 ld24 r0,#0
23 ld24 r0,#0
[all …]
Dsigned-relocs.s5 seth r0, #shigh(0x87654321)
6 add3 r0, r0, #low(0x87654321)
7 seth r0, #SHIGH(0x87654321)
8 add3 r0, r0, #LOW(0x87654321)
9 seth r0, #shigh(0x1234ffff)
10 add3 r0, r0, #low(0x1234ffff)
11 seth r0, #SHIGH(0x1234ffff)
12 add3 r0, r0, #LOW(0x1234ffff)
14 seth r0, #high(0x87654321)
15 or3 r0, r0, #low(0x87654321)
[all …]
Dsigned-relocs.d10 0: d0 c0 87 65 seth r0,#0x8765
11 4: 80 a0 43 21 add3 r0,r0,#17185
12 8: d0 c0 87 65 seth r0,#0x8765
13 c: 80 a0 43 21 add3 r0,r0,#17185
14 10: d0 c0 12 35 seth r0,#0x1235
15 14: 80 a0 ff ff add3 r0,r0,#-1
16 18: d0 c0 12 35 seth r0,#0x1235
17 1c: 80 a0 ff ff add3 r0,r0,#-1
18 20: d0 c0 87 65 seth r0,#0x8765
19 24: 80 e0 43 21 or3 r0,r0,#0x4321
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/lm32/
Dinsn.d10 0: b4 00 f8 00 add ba,r0,r0
11 4: b7 e0 00 00 add r0,ba,r0
12 8: b4 1f 00 00 add r0,r0,ba
15 14: 34 00 80 00 mvi r0,-32768
16 18: 34 00 7f ff mvi r0,32767
17 1c: 37 e0 00 00 addi r0,ba,0
18 20: 37 e0 80 00 addi r0,ba,-32768
19 24: 37 e0 7f ff addi r0,ba,32767
23 34: a0 00 f8 00 and ba,r0,r0
24 38: a3 e0 00 00 and r0,ba,r0
[all …]
Dinsn.s2 \insn r31, r0, r0
3 \insn r0, r31, r0
4 \insn r0, r0, r31
9 \insn r0, r0, 0
10 \insn r0, r0, -32768
11 \insn r0, r0, 32767
12 \insn r0, r31, 0
13 \insn r0, r31, -32768
14 \insn r0, r31, 32767
15 \insn r31, r0, 0
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/iq2000/
Dallinsn.d10 0: 00 00 00 20 add r0,r0,r0
13 4: 20 00 ff fc addi r0,r0,0xfffc
16 8: 24 00 00 04 addiu r0,r0,0x4
19 c: 00 00 00 21 addu r0,r0,r0
22 10: 00 00 00 29 ado16 r0,r0,r0
25 14: 00 00 00 24 and r0,r0,r0
28 18: 30 00 de ad andi r0,r0,0xdead
31 1c: b0 00 00 00 andoi r0,r0,0x0
34 20: fc 00 00 00 andoui r0,r0,0x0
37 24: 00 00 00 2d mrgb r0,r0,r0,0x0
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/nds32/
Dsys-reg.s2 mfsr $r0 ,$CPU_VER
3 mfsr $r0 ,$CORE_ID
4 mfsr $r0 ,$ICM_CFG
5 mfsr $r0 ,$DCM_CFG
6 mfsr $r0 ,$MMU_CFG
7 mfsr $r0 ,$MSC_CFG
9 mfsr $r0 ,$PSW
10 mfsr $r0 ,$IPSW
11 mfsr $r0 ,$P_IPSW
12 mfsr $r0 ,$IVB
[all …]
Dsys-reg.d11 0+0000 <[^>]*> mfsr \$r0, \$CPU_VER
12 0+0004 <[^>]*> mfsr \$r0, \$CORE_ID
13 0+0008 <[^>]*> mfsr \$r0, \$ICM_CFG
14 0+000c <[^>]*> mfsr \$r0, \$DCM_CFG
15 0+0010 <[^>]*> mfsr \$r0, \$MMU_CFG
16 0+0014 <[^>]*> mfsr \$r0, \$MSC_CFG
17 0+0018 <[^>]*> mfsr \$r0, \$PSW
18 0+001c <[^>]*> mfsr \$r0, \$IPSW
19 0+0020 <[^>]*> mfsr \$r0, \$P_IPSW
20 0+0024 <[^>]*> mfsr \$r0, \$IVB
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/
Dbranch.d10 0: 3d 00 20 b4 bla %r0,%r1,0x000000f8 // 0xf8
11 4: 00 00 00 a0 shl %r0,%r0,%r0
13 c: 00 00 00 a0 shl %r0,%r0,%r0
15 14: 00 00 00 a0 shl %r0,%r0,%r0
17 1c: 00 00 00 a0 shl %r0,%r0,%r0
18 20: 00 00 00 40 bri %r0
19 24: 00 00 00 a0 shl %r0,%r0,%r0
21 2c: 00 00 00 a0 shl %r0,%r0,%r0
23 34: 00 00 00 a0 shl %r0,%r0,%r0
25 3c: 00 00 00 a0 shl %r0,%r0,%r0
[all …]

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