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Searched refs:regs (Results 1 – 25 of 115) sorted by relevance

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/toolchain/binutils/binutils-2.25/gas/config/
Dtc-metag.c281 parse_gp_regs_list (const char *line, const metag_reg **regs, size_t count, in parse_gp_regs_list() argument
328 regs[i] = reg; in parse_gp_regs_list()
346 parse_gp_regs (const char *line, const metag_reg **regs, size_t count) in parse_gp_regs() argument
351 l = parse_gp_regs_list (l, regs, count, &regs_read); in parse_gp_regs()
362 parse_fpu_regs (const char *line, const metag_reg **regs, size_t count) in parse_fpu_regs() argument
367 l = parse_gp_regs_list (l, regs, count, &regs_read); in parse_fpu_regs()
376 if (regs[i]->unit != UNIT_FX) in parse_fpu_regs()
418 parse_pair_gp_regs (const char *line, const metag_reg **regs) in parse_pair_gp_regs() argument
422 l = parse_gp_regs (line, regs, 2); in parse_pair_gp_regs()
426 l = parse_gp_regs (line, regs, 1); in parse_pair_gp_regs()
[all …]
Dtc-i386.c249 const reg_entry *regs; member
2710 fprintf (stdout, "%s\n", x->op[j].regs->reg_name); in pi()
3383 if (register_number (i.op[x].regs) != x) in process_immext()
3385 register_prefix, i.op[x].regs->reg_name, x + 1, in process_immext()
3692 && (i.op[0].regs->reg_flags & RegRex64) != 0) in md_assemble()
3694 && (i.op[1].regs->reg_flags & RegRex64) != 0) in md_assemble()
3706 && (i.op[x].regs->reg_flags & RegRex64) == 0) in md_assemble()
3709 if (i.op[x].regs->reg_num > 3) in md_assemble()
3712 register_prefix, i.op[x].regs->reg_name); in md_assemble()
3718 i.op[x].regs = i.op[x].regs + 8; in md_assemble()
[all …]
Dtc-i386-intel.c222 && rreg != i.op[this_operand].regs) in i386_intel_check()
272 if (i.op[this_operand].regs) in i386_intel_simplify_register()
283 i.op[this_operand].regs = i386_regtab + reg_num; in i386_intel_simplify_register()
331 ? i.op[this_operand].regs : NULL); in i386_intel_simplify()
725 if (i.op[this_operand].regs in i386_intel_operand()
797 if (i.op[this_operand].regs) in i386_intel_operand()
808 temp = i.op[this_operand].regs->reg_type; in i386_intel_operand()
/toolchain/binutils/binutils-2.25/opcodes/
Dmsp430-dis.c140 int regs = 0, regd = 0; in msp430_singleoperand() local
149 regs = (insn & 0x0f00) >> 8; in msp430_singleoperand()
161 if (regs != 2 && regs != 3 && regs != 1) in msp430_singleoperand()
374 int regs = 0, regd = 0; in msp430_doubleoperand() local
383 regs = (insn & 0x0f00) >> 8; in msp430_doubleoperand()
404 if (regd != regs || as != ad) in msp430_doubleoperand()
495 if (regs == 3) in msp430_doubleoperand()
504 sprintf (op1, "r%d", regs); in msp430_doubleoperand()
509 * cycles = print_as2_reg_name (regs, op1, comm1, 1, 1, regs == 0 ? 3 : 2); in msp430_doubleoperand()
513 if (regs == 0) in msp430_doubleoperand()
[all …]
Dmmix-opc.c98 {"fcmp", O (1), OP (regs), N},
101 {"fun", O (2), OP (regs), N},
102 {"feql", O (3), OP (regs), N},
105 {"fadd", O (4), OP (regs), N},
109 {"fsub", O (6), OP (regs), N},
113 {"fmul", O (16), OP (regs), N},
114 {"fcmpe", O (17), OP (regs), N},
117 {"fune", O (18), OP (regs), N},
118 {"feqle", O (19), OP (regs), N},
121 {"fdiv", O (20), OP (regs), N},
[all …]
Davr-dis.c52 char *opcode_str, char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr) in avr_operand() argument
61 if (regs) in avr_operand()
70 if (regs) in avr_operand()
81 if (regs) in avr_operand()
88 if (regs) in avr_operand()
377 int regs = REGISTER_P (*constraints); in print_insn_avr() local
383 *comment1 ? comment2 : comment1, regs, &sym_op2, &sym_addr2); in print_insn_avr()
Dv850-dis.c443 int *regs; in disassemble() local
450 case 0xffe00001: regs = list12_regs; break; in disassemble()
461 switch (regs[ i ]) in disassemble()
463 default: mask |= (1 << regs[ i ]); break; in disassemble()
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/
Dmips16-intermix-2.s7 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
25 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
41 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
58 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
74 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
91 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
107 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
124 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
140 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
157 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
[all …]
Djr-to-b-1.s8 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
26 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
Djr-to-b-2.s8 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
26 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
Djalx-2-main.s15 .frame $fp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
43 .frame $fp,32,$31 # vars= 0, regs= 2/0, args= 16, gp= 8
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dmips16-intermix.s7 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
25 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
41 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
58 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
74 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
91 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
107 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
124 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
140 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
157 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
[all …]
Delf_e_flags.s10 .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, extra= 0
27 .frame $sp,40,$31 # vars= 0, regs= 1/0, args= 32, extra= 0
Dlineno.s13 .frame $fp,24,$31 # vars= 16, regs= 2/0, args= 0, extra= 0
44 .frame $fp,24,$31 # vars= 16, regs= 1/0, args= 0, extra= 0
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
Dregs.pl100 @regs = ( "rsc", "bsp", "bspstore", "rnat", "ccv", "unat", "fpsr", "itc",
102 foreach $i (@regs) {
122 @regs = ( "dcr", "itm", "iva", "pta", "ipsr", "isr", "iip",
128 foreach $i (@regs) {
142 @regs = ("pmc", "pmd", "pkr", "rr", "ibr", "dbr", "CPUID", "cpuid");
145 foreach $i (@regs) {
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
Dneon-ins.s5 .irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
6 \macro_name \regs b \index \reg
11 .irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
12 \macro_name \regs h \index \reg
17 .irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
18 \macro_name \regs s \index \reg
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dhlebad.s41 # Tests for op imm16 regs/m16
61 # Tests for op imm8 regs/m16
114 # Tests for op regs regs/m16
115 # Tests for op regs/m16 regs
160 # Tests for op regs, regs/m16
190 # Tests for op regs/m16
260 # Tests for op imm16 regs/m16
280 # Tests for op imm8 regs/m16
333 # Tests for op regs regs/m16
334 # Tests for op regs/m16 regs
[all …]
Dhlebad.l397 [ ]*41[ ]+\# Tests for op imm16 regs/m16
420 [ ]*61[ ]+\# Tests for op imm8 regs/m16
473 [ ]*114[ ]+\# Tests for op regs regs/m16
477 [ ]*115[ ]+\# Tests for op regs/m16 regs
522 [ ]*160[ ]+\# Tests for op regs, regs/m16
555 [ ]*190[ ]+\# Tests for op regs/m16
628 [ ]*260[ ]+\# Tests for op imm16 regs/m16
648 [ ]*280[ ]+\# Tests for op imm8 regs/m16
704 [ ]*333[ ]+\# Tests for op regs regs/m16
705 [ ]*334[ ]+\# Tests for op regs/m16 regs
[all …]
Dx86-64-hlebad.s50 # Tests for op imm16 regs/m16
80 # Tests for op imm8 regs/m16
143 # Tests for op regs regs/m16
144 # Tests for op regs/m16 regs
212 # Tests for op regs, regs/m16
252 # Tests for op regs/m16
341 # Tests for op imm16 regs/m16
371 # Tests for op imm8 regs/m16
434 # Tests for op regs regs/m16
435 # Tests for op regs/m16 regs
[all …]
Dx86-64-hlebad.l522 [ ]*50[ ]+\# Tests for op imm16 regs/m16
555 [ ]*80[ ]+\# Tests for op imm8 regs/m16
621 [ ]*143[ ]+\# Tests for op regs regs/m16
622 [ ]*144[ ]+\# Tests for op regs/m16 regs
693 [ ]*212[ ]+\# Tests for op regs, regs/m16
736 [ ]*252[ ]+\# Tests for op regs/m16
828 [ ]*341[ ]+\# Tests for op imm16 regs/m16
861 [ ]*371[ ]+\# Tests for op imm8 regs/m16
927 [ ]*434[ ]+\# Tests for op regs regs/m16
928 [ ]*435[ ]+\# Tests for op regs/m16 regs
[all …]
/toolchain/binutils/binutils-2.25/libiberty/
Dregex.c75 # define re_match_2(bufp, string1, size1, string2, size2, pos, regs, stop) \ argument
76 __re_match_2 (bufp, string1, size1, string2, size2, pos, regs, stop)
77 # define re_match(bufp, string, size, pos, regs) \ argument
78 __re_match (bufp, string, size, pos, regs)
79 # define re_search(bufp, string, size, startpos, range, regs) \ argument
80 __re_search (bufp, string, size, startpos, range, regs)
84 # define re_search_2(bufp, st1, s1, st2, s2, startpos, range, regs, stop) \ argument
85 __re_search_2 (bufp, st1, s1, st2, s2, startpos, range, regs, stop)
418 struct re_registers *regs,
424 struct re_registers *regs, int stop);
[all …]
/toolchain/binutils/binutils-2.25/include/
Dxregex2.h464 struct re_registers *regs);
471 int start, int range, struct re_registers *regs,
478 int length, int start, struct re_registers *regs);
484 int start, struct re_registers *regs, int stop);
500 struct re_registers *regs,
/toolchain/binutils/binutils-2.25/binutils/
Dod-macho.c1679 unsigned int regs; in dump_unwind_encoding_x86() local
1682 regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS; in dump_unwind_encoding_x86()
1684 if (regs != 0) in dump_unwind_encoding_x86()
1693 unsigned int reg = (regs >> (i * 3)) & 0x7; in dump_unwind_encoding_x86()
1706 unsigned int regs[6]; in dump_unwind_encoding_x86() local
1735 DO_PERM (regs[0], 120); in dump_unwind_encoding_x86()
1736 DO_PERM (regs[1], 24); in dump_unwind_encoding_x86()
1737 DO_PERM (regs[2], 6); in dump_unwind_encoding_x86()
1738 DO_PERM (regs[3], 2); in dump_unwind_encoding_x86()
1739 DO_PERM (regs[4], 1); in dump_unwind_encoding_x86()
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dmacro1.s2 .macro popret regs argument
3 ldmia sp!, {\regs, pc}
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/microblaze/
Dreloc_weaksym.s7 .frame r19,8,r15 # vars= 0, regs= 1, args= 0
26 .frame r19,32,r15 # vars= 0, regs= 1, args= 24

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