Home
last modified time | relevance | path

Searched refs:s0 (Results 1 – 25 of 129) sorted by relevance

123456

/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dvfp1xD_t2.s9 @ Most of these tests deliberatly use s0/r0 to avoid setting
16 fcmpes s0, s0
17 fcmpezs s0
18 fcmps s0, s0
19 fcmpzs s0
23 fabss s0, s0
24 fcpys s0, s0
25 fnegs s0, s0
26 fsqrts s0, s0
30 fadds s0, s0, s0
[all …]
Dvfp1xD.s6 @ Most of these tests deliberatly use s0/r0 to avoid setting
13 fcmpes s0, s0
14 fcmpezs s0
15 fcmps s0, s0
16 fcmpzs s0
20 fabss s0, s0
21 fcpys s0, s0
22 fnegs s0, s0
23 fsqrts s0, s0
27 fadds s0, s0, s0
[all …]
Dvfp1xD.d11 0+004 <[^>]*> eeb40ac0 (vcmpe\.f32|fcmpes) s0, s0
12 0+008 <[^>]*> eeb50ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0)
13 0+00c <[^>]*> eeb40a40 (vcmp\.f32|fcmps) s0, s0
14 0+010 <[^>]*> eeb50a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
15 0+014 <[^>]*> eeb00ac0 (vabs\.f32|fabss) s0, s0
16 0+018 <[^>]*> eeb00a40 (vmov\.f32|fcpys) s0, s0
17 0+01c <[^>]*> eeb10a40 (vneg\.f32|fnegs) s0, s0
18 0+020 <[^>]*> eeb10ac0 (vsqrt\.f32|fsqrts) s0, s0
19 0+024 <[^>]*> ee300a00 (vadd\.f32|fadds) s0, s0, s0
20 0+028 <[^>]*> ee800a00 (vdiv\.f32|fdivs) s0, s0, s0
[all …]
Dvfp-neon-syntax.d8 0[0-9a-f]+ <[^>]+> eeb00a60 (vmov\.f32|fcpys) s0, s1
10 0[0-9a-f]+ <[^>]+> eeb50a00 (vmov\.f32|fconsts) s0, #80.*
13 0[0-9a-f]+ <[^>]+> ee001a10 (vmov|fmsr) s0, r1
15 0[0-9a-f]+ <[^>]+> ec442a10 (vmov s0, s1, r2, r4|fmsrr {s0, s1}, r2, r4)
16 0[0-9a-f]+ <[^>]+> 0eb00a60 (vmoveq\.f32|fcpyseq) s0, s1
18 0[0-9a-f]+ <[^>]+> 0eb50a00 (vmoveq\.f32|fconstseq) s0, #80.*
21 0[0-9a-f]+ <[^>]+> 0e001a10 (vmoveq|fmsreq) s0, r1
23 0[0-9a-f]+ <[^>]+> 0c442a10 (vmoveq s0, s1, r2, r4|fmsrreq {s0, s1}, r2, r4)
24 0[0-9a-f]+ <[^>]+> eeb10ae0 (vsqrt\.f32|fsqrts) s0, s1
26 0[0-9a-f]+ <[^>]+> 0eb10ae0 (vsqrteq.f32|fsqrtseq) s0, s1
[all …]
Dvfp1xD_t2.d11 0+004 <[^>]*> eeb4 0ac0 (vcmpe\.f32|fcmpes) s0, s0
12 0+008 <[^>]*> eeb5 0ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0)
13 0+00c <[^>]*> eeb4 0a40 (vcmp\.f32|fcmps) s0, s0
14 0+010 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
15 0+014 <[^>]*> eeb0 0ac0 (vabs\.f32|fabss) s0, s0
16 0+018 <[^>]*> eeb0 0a40 (vmov\.f32|fcpys) s0, s0
17 0+01c <[^>]*> eeb1 0a40 (vneg\.f32|fnegs) s0, s0
18 0+020 <[^>]*> eeb1 0ac0 (vsqrt\.f32|fsqrts) s0, s0
19 0+024 <[^>]*> ee30 0a00 (vadd\.f32|fadds) s0, s0, s0
20 0+028 <[^>]*> ee80 0a00 (vdiv\.f32|fdivs) s0, s0, s0
[all …]
Dvfp-neon-syntax_t2.d8 0[0-9a-f]+ <[^>]+> eeb0 0a60 (vmov\.f32|fcpys) s0, s1
10 0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmov\.f32|fconsts) s0, #80.*
13 0[0-9a-f]+ <[^>]+> ee00 1a10 (vmov|fmsr) s0, r1
15 0[0-9a-f]+ <[^>]+> ec44 2a10 (vmov s0, s1, r2, r4|fmsrr {s0, s1}, r2, r4)
17 0[0-9a-f]+ <[^>]+> eeb0 0a60 (vmoveq\.f32|fcpyseq) s0, s1
19 0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmoveq\.f32|fconstseq) s0, #80.*
23 0[0-9a-f]+ <[^>]+> ee00 1a10 (vmoveq|fmsreq) s0, r1
25 0[0-9a-f]+ <[^>]+> ec44 2a10 (vmoveq s0, s1, r2, r4|fmsrreq {s0, s1}, r2, r4)
26 0[0-9a-f]+ <[^>]+> eeb1 0ae0 (vsqrt\.f32|fsqrts) s0, s1
29 0[0-9a-f]+ <[^>]+> eeb1 0ae0 (vsqrteq\.f32|fsqrtseq) s0, s1
[all …]
Dvfma1.d13 00000000 <[^>]*> ee000a00 vmla.f32 s0, s0, s0
17 00000010 <[^>]*> eea00a00 vfma.f32 s0, s0, s0
21 00000020 <[^>]*> ee000a40 vmls.f32 s0, s0, s0
25 00000030 <[^>]*> eea00a40 vfms.f32 s0, s0, s0
29 00000040 <[^>]*> ee100a40 vnmla.f32 s0, s0, s0
31 00000048 <[^>]*> ee900a40 vfnma.f32 s0, s0, s0
33 00000050 <[^>]*> ee100a00 vnmls.f32 s0, s0, s0
35 00000058 <[^>]*> ee900a00 vfnms.f32 s0, s0, s0
Dvfma1.s6 .inst 0xee000a00 @ VFP vmla.f32 s0,s0,s0
12 .inst 0xeea00a00 @ VFP vfma.f32 s0,s0,s0
18 .inst 0xee000a40 @ VFP vmls.F32 s0,s0,s0
24 .inst 0xeea00a40 @ VFP vfms.F32 s0,s0,s0
30 .inst 0xee100a40 @ VFP vnmla.F32 s0,s0,s0
34 .inst 0xee900a40 @ VFP vfnma.F32 s0,s0,s0
38 .inst 0xee100a00 @ VFP vnmls.F32 s0,s0,s0
42 .inst 0xee900a00 @ VFP vfnms.F32 s0,s0,s0
Darmv8-a+fp.s7 vseleq.f32 s0, s0, s0
15 vmaxnm.f32 s0, s0, s0
23 vminnm.f32 s0, s0, s0
31 vcvta.s32.f32 s0, s0
35 vcvta.s32.f64 s0, d0
39 vrintz.f32 s0, s0
42 vrinta.f32 s0, s0
53 vcvtt.f16.f64 s0, d0
57 vcvtt.f64.f16 d0, s0
63 vseleq.f32 s0, s0, s0
[all …]
Dvfp-neon-syntax-inc.s10 vmov\cond\f32 s0,s1
12 vmov\cond\f32 s0,#0.25
16 vmov\cond s0,r1
18 vmov\cond s0,s1,r2,r4
27 \op\cond\f32 s0,s1
38 \op\cond\f32 s0,s1,s2
49 \op\cond\f32 s0,#0
82 vcvtz\cond\s32\f32 s0,s1
83 vcvtz\cond\u32\f32 s0,s1
84 vcvtz\cond\s32\f64 s0,d1
[all …]
Darmv8-a+fp.d8 0[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0
16 0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
24 0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
32 0[0-9a-f]+ <[^>]+> febc0ac0 vcvta.s32.f32 s0, s0
36 0[0-9a-f]+ <[^>]+> febc0bc0 vcvta.s32.f64 s0, d0
40 0[0-9a-f]+ <[^>]+> eeb60ac0 vrintz.f32 s0, s0
43 0[0-9a-f]+ <[^>]+> feb80a40 vrinta.f32 s0, s0
54 0[0-9a-f]+ <[^>]+> eeb30bc0 vcvtt.f16.f64 s0, d0
58 0[0-9a-f]+ <[^>]+> eeb20bc0 vcvtt.f64.f16 d0, s0
62 0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
[all …]
Dvfp-fma-arm.d8 0[0-9a-f]+ <[^>]+> eea00a81 vfma\.f32 s0, s1, s2
10 0[0-9a-f]+ <[^>]+> 0ea00a81 vfmaeq\.f32 s0, s1, s2
12 0[0-9a-f]+ <[^>]+> eea00ac1 vfms\.f32 s0, s1, s2
14 0[0-9a-f]+ <[^>]+> 0ea00ac1 vfmseq\.f32 s0, s1, s2
16 0[0-9a-f]+ <[^>]+> ee900ac1 vfnma\.f32 s0, s1, s2
18 0[0-9a-f]+ <[^>]+> 0e900ac1 vfnmaeq\.f32 s0, s1, s2
20 0[0-9a-f]+ <[^>]+> ee900a81 vfnms\.f32 s0, s1, s2
22 0[0-9a-f]+ <[^>]+> 0e900a81 vfnmseq\.f32 s0, s1, s2
Dvfp-fma-thumb.d8 0[0-9a-f]+ <[^>]+> eea0 0a81 vfma\.f32 s0, s1, s2
11 0[0-9a-f]+ <[^>]+> eea0 0a81 vfmaeq\.f32 s0, s1, s2
13 0[0-9a-f]+ <[^>]+> eea0 0ac1 vfms\.f32 s0, s1, s2
16 0[0-9a-f]+ <[^>]+> eea0 0ac1 vfmseq\.f32 s0, s1, s2
18 0[0-9a-f]+ <[^>]+> ee90 0ac1 vfnma\.f32 s0, s1, s2
21 0[0-9a-f]+ <[^>]+> ee90 0ac1 vfnmaeq\.f32 s0, s1, s2
23 0[0-9a-f]+ <[^>]+> ee90 0a81 vfnms\.f32 s0, s1, s2
26 0[0-9a-f]+ <[^>]+> ee90 0a81 vfnmseq\.f32 s0, s1, s2
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
Dopc-f.s6 fma.s0 f4 = f5, f6, f7
12 fma.s.s0 f4 = f5, f6, f7
18 fma.d.s0 f4 = f5, f6, f7
24 fpma.s0 f4 = f5, f6, f7
30 fms.s0 f4 = f5, f6, f7
36 fms.s.s0 f4 = f5, f6, f7
42 fms.d.s0 f4 = f5, f6, f7
48 fpms.s0 f4 = f5, f6, f7
54 fnma.s0 f4 = f5, f6, f7
60 fnma.s.s0 f4 = f5, f6, f7
[all …]
Dopc-f.d11 6: 40 38 14 0c 40 00 fma\.s0 f4=f5,f6,f7
14 16: 40 38 14 0c 40 00 fma\.s0 f4=f5,f6,f7
26 56: 40 38 14 0c 44 00 fma\.s\.s0 f4=f5,f6,f7
29 66: 40 38 14 0c 44 00 fma\.s\.s0 f4=f5,f6,f7
41 a6: 40 38 14 0c 48 00 fma\.d\.s0 f4=f5,f6,f7
44 b6: 40 38 14 0c 48 00 fma\.d\.s0 f4=f5,f6,f7
56 f6: 40 38 14 0c 4c 00 fpma\.s0 f4=f5,f6,f7
59 106: 40 38 14 0c 4c 00 fpma\.s0 f4=f5,f6,f7
71 146: 40 38 14 0c 50 00 fms\.s0 f4=f5,f6,f7
74 156: 40 38 14 0c 50 00 fms\.s0 f4=f5,f6,f7
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dmips16e-save.d11 4:[ ]+64a3[ ]+save[ ]+24,s0
13 8:[ ]+64b5[ ]+save[ ]+40,s0-s1
14 a:[ ]+64e6[ ]+save[ ]+48,ra,s0
16 e:[ ]+64f8[ ]+save[ ]+64,ra,s0-s1
17 10:[ ]+64f9[ ]+save[ ]+72,ra,s0-s1
18 12:[ ]+64fa[ ]+save[ ]+80,ra,s0-s1
19 14:[ ]+64fb[ ]+save[ ]+88,ra,s0-s1
20 16:[ ]+64f0[ ]+save[ ]+128,ra,s0-s1
23 20:[ ]+f010 64b3[ ]+save[ ]+152,s0-s1
27 30:[ ]+f700 64bb[ ]+save[ ]+88,s0-s8
[all …]
Dmicromips.s1065 lwm $s0, $ra, 12<<2($29)
1066 lwm $s0, $s1, $ra, 12<<2($29)
1067 lwm $s0-$s1, $ra, 12<<2($29)
1068 lwm $s0, $s1, $s2, $ra, 12<<2($29)
1069 lwm $s0-$s2, $ra, 12<<2($29)
1070 lwm $s0, $s1, $s2, $s3, $ra, 12<<2($29)
1071 lwm $s0-$s3, $ra, 12<<2($29)
1072 lwm $s0, $ra, ($29)
1073 lwm $s0, $ra, 0($29)
1074 lwm $s0, $ra, 1<<2($29)
[all …]
Dloc-swap-dis.d11 [0-9a-f]+ <[^>]*> 02002021 move a0,s0
15 [0-9a-f]+ <[^>]*> 0200f821 move ra,s0
17 [0-9a-f]+ <[^>]*> 02002021 move a0,s0
18 [0-9a-f]+ <[^>]*> 0200f821 move ra,s0
21 [0-9a-f]+ <[^>]*> 02002021 move a0,s0
24 [0-9a-f]+ <[^>]*> 0200f821 move ra,s0
29 [0-9a-f]+ <[^>]*> 02002021 move a0,s0
30 [0-9a-f]+ <[^>]*> 0200f821 move ra,s0
Dmipsr6@loc-swap-dis.d11 [0-9a-f]+ <[^>]*> 02002021 move a0,s0
15 [0-9a-f]+ <[^>]*> 0200f821 move ra,s0
17 [0-9a-f]+ <[^>]*> 02002021 move a0,s0
18 [0-9a-f]+ <[^>]*> 0200f821 move ra,s0
21 [0-9a-f]+ <[^>]*> 02002021 move a0,s0
24 [0-9a-f]+ <[^>]*> 0200f821 move ra,s0
29 [0-9a-f]+ <[^>]*> 02002021 move a0,s0
30 [0-9a-f]+ <[^>]*> 0200f821 move ra,s0
Dmicromips@loc-swap-dis.d11 [0-9a-f]+ <[^>]*> 0c90 move a0,s0
15 [0-9a-f]+ <[^>]*> 0ff0 move ra,s0
17 [0-9a-f]+ <[^>]*> 0c90 move a0,s0
18 [0-9a-f]+ <[^>]*> 0ff0 move ra,s0
21 [0-9a-f]+ <[^>]*> 0c90 move a0,s0
24 [0-9a-f]+ <[^>]*> 0ff0 move ra,s0
27 [0-9a-f]+ <[^>]*> 0c90 move a0,s0
31 [0-9a-f]+ <[^>]*> 0ff0 move ra,s0
Dmips16@loc-swap-dis.d11 [0-9a-f]+ <[^>]*> 6790 move a0,s0
15 [0-9a-f]+ <[^>]*> 65f8 move ra,s0
17 [0-9a-f]+ <[^>]*> 6790 move a0,s0
18 [0-9a-f]+ <[^>]*> 65f8 move ra,s0
21 [0-9a-f]+ <[^>]*> 6790 move a0,s0
24 [0-9a-f]+ <[^>]*> 65f8 move ra,s0
29 [0-9a-f]+ <[^>]*> 6790 move a0,s0
30 [0-9a-f]+ <[^>]*> 65f8 move ra,s0
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
Dfloatdp2.d8 0: 1e2f08e0 fmul s0, s7, s15
9 4: 1e2f18e0 fdiv s0, s7, s15
10 8: 1e2f28e0 fadd s0, s7, s15
11 c: 1e2f38e0 fsub s0, s7, s15
12 10: 1e2f48e0 fmax s0, s7, s15
13 14: 1e2f58e0 fmin s0, s7, s15
14 18: 1e2f68e0 fmaxnm s0, s7, s15
15 1c: 1e2f78e0 fminnm s0, s7, s15
16 20: 1e2f88e0 fnmul s0, s7, s15
Dfpmov.s6 fmov s0, 12.0
7 fmov s0, 1.2e1
8 fmov s0, 0x41400000
9 fmov s0, -12.0
10 fmov s0, -1.2e1
11 fmov s0, 0xc1400000
17 fmov s0, 0x3e780000
Dfpmov.d8 0: 1e251000 fmov s0, #1\.200000000000000000e\+01
9 4: 1e251000 fmov s0, #1\.200000000000000000e\+01
10 8: 1e251000 fmov s0, #1\.200000000000000000e\+01
11 c: 1e351000 fmov s0, #-1\.200000000000000000e\+01
12 10: 1e351000 fmov s0, #-1\.200000000000000000e\+01
13 14: 1e351000 fmov s0, #-1\.200000000000000000e\+01
19 2c: 1e29f000 fmov s0, #2\.421875000000000000e-01
/toolchain/binutils/binutils-2.25/gas/config/
Dbfin-parse.y255 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1)) in check_multiply_halfregs()
256 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0))) in check_multiply_halfregs()
336 aa->s0.regno |= (ab->s0.regno & CODE_MASK); in check_macfuncs()
453 struct { int r0; int s0; int x0; int aop; } modcodes; member
754 h00 = IS_H ($1.s0);
765 h01 = IS_H ($1.s0);
769 &$1.dst, op0, &$1.s0, &$1.s1, w0);
789 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
790 dst, $4.op, &$1.s0, &$1.s1, $4.w);
918 $$ = DSP32ALU (17, 0, &$1, &$7, &reg7, &reg7, $12.s0, $12.x0, 0);
[all …]

123456