Searched refs:thumb32_opcodes (Results 1 – 9 of 9) sorted by relevance
197 (thumb32_opcodes): Likewise.210 (thumb32_opcodes): Likewise.215 (thumb32_opcodes): Likewise.688 (thumb32_opcodes): Likewise.
336 (thumb32_opcodes): Likewise.346 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.352 (thumb32_opcodes): Likewise.
599 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn769 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
372 (thumb32_opcodes): Ditto.703 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
244 (thumb32_opcodes): Add udf.w.245 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.1134 (thumb32_opcodes): Likewise.
381 * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.400 (arm_opcodes, thumb32_opcodes): Remove coprocessor insns.766 (thumb32_opcodes): New table.
1482 static const struct opcode32 thumb32_opcodes[] = variable3965 for (insn = thumb32_opcodes; insn->assembler; insn++) in print_insn_thumb32()
1197 * arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W1605 * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd,
1320 * arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses.