Searched refs:vex (Results 1 – 10 of 10) sorted by relevance
3117 vex; variable12391 switch (vex.prefix) in get_valid_dis386()12477 switch (vex.length) in get_valid_dis386()12516 vex.w = *codep & 0x80; in get_valid_dis386()12517 if (vex.w && address_mode == mode_64bit) in get_valid_dis386()12520 vex.register_specifier = (~(*codep >> 3)) & 0xf; in get_valid_dis386()12522 && vex.register_specifier > 0x7) in get_valid_dis386()12528 vex.length = (*codep & 0x4) ? 256 : 128; in get_valid_dis386()12532 vex.prefix = 0; in get_valid_dis386()12535 vex.prefix = DATA_PREFIX_OPCODE; in get_valid_dis386()[all …]
587 unsigned int vex:2; member
163 * i386-dis.c (get_valid_dis386): Set vex.w to 0 for VEX C5165 (print_insn): Don't set vex.w here.169 * i386-dis.c (print_insn): Set vex.w to 0.509 when vex.w is set. Third source operand is decoded with688 (i386_opcode_modifier): Change vex to 2 bits. Remove vex256.
701 (vex): Likewise.778 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
738 (vex table): Added entries for VEX_W_3A48_P_2 and
595 (struct vex): Add fields evex, r, v, mask_register_specifier,
332 vex_prefix vex; member3066 if (i.vex.register_specifier) in build_vex_prefix()3069 ~register_number (i.vex.register_specifier) & 0xf; in build_vex_prefix()3070 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); in build_vex_prefix()3105 if (i.tm.opcode_modifier.vex == VEXScalar) in build_vex_prefix()3108 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; in build_vex_prefix()3136 i.vex.length = 2; in build_vex_prefix()3137 i.vex.bytes[0] = 0xc5; in build_vex_prefix()3141 i.vex.bytes[1] = (r << 7 in build_vex_prefix()3151 i.vex.length = 3; in build_vex_prefix()[all …]
1296 (_i386_insn): Add vex.1306 are true. Call build_vex_prefix if vex is true.
2124 * config/tc-i386.c (build_vex_prefix): Set i.vex.bytes[0] to
593 * config/tc-i386.c (build_vex_prefix): Check vex == 2 instead