| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| D | thumb2_vpool_be.d | 5 #name: Thumb2 vldr with immediate constant
11 00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 <thumb2_ldr\+0x40>
12 00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 <thumb2_ldr\+0x40>
13 00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 <thumb2_ldr\+0x40>
14 0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] ; 00000040 <thumb2_ldr\+0x40>
15 00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 <thumb2_ldr\+0x44>
16 00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 <thumb2_ldr\+0x44>
17 00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 <thumb2_ldr\+0x44>
18 0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] ; 00000044 <thumb2_ldr\+0x44>
19 00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 <thumb2_ldr\+0x48>
[all …]
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| D | thumb2_vpool.d | 5 #name: Thumb2 vldr with immediate constant
10 00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 <thumb2_ldr\+0x40>
11 00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 <thumb2_ldr\+0x40>
12 00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 <thumb2_ldr\+0x40>
13 0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] ; 00000040 <thumb2_ldr\+0x40>
14 00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 <thumb2_ldr\+0x44>
15 00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 <thumb2_ldr\+0x44>
16 00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 <thumb2_ldr\+0x44>
17 0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] ; 00000044 <thumb2_ldr\+0x44>
18 00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 <thumb2_ldr\+0x48>
[all …]
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| D | vldconst_be.d | 2 #name: ARM vldr with immediate constant (Big Endian)
10 00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 <foo\+0x40>
11 00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 <foo\+0x40>
12 00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] ; 00000040 <foo\+0x40>
13 0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] ; 00000040 <foo\+0x40>
14 00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 <foo\+0x44>
15 00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 <foo\+0x44>
16 00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] ; 00000044 <foo\+0x44>
17 0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] ; 00000044 <foo\+0x44>
18 00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 <foo\+0x48>
[all …]
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| D | vldconst.d | 2 #name: ARM vldr with immediate constant
9 00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 <foo\+0x40>
10 00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 <foo\+0x40>
11 00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] ; 00000040 <foo\+0x40>
12 0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] ; 00000040 <foo\+0x40>
13 00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 <foo\+0x44>
14 00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 <foo\+0x44>
15 00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] ; 00000044 <foo\+0x44>
16 0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] ; 00000044 <foo\+0x44>
17 00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 <foo\+0x48>
[all …]
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| D | thumb2_vpool.s | 9 vldr \regtype\regindex, \const
12 # Thumb-2 support vldr literal pool also.
51 vldr d1, =0x0000fff000000000 define
57 vldr d1, =0x0000fff000000000 define
61 vldr d1, =0x0000fff000000000 define
62 vldr s2, =0xff000000
64 vldr d3, =0x0000fff000000001 define
66 vldr s4, =0xff000001
68 vldr d5, =0x0000fff000000001 define
70 vldr d6, =0x0000fff000000002 define
[all …]
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| D | vldconst.s | 1 @ Test file for ARM/GAS -- vldr reg, =... expressions.
10 vldr \regtype\regindex, \const
100 vldr d1, =0x0000fff000000000 define
106 vldr d1, =0x0000fff000000000 define
110 vldr d1, =0x0000fff000000000 define
111 vldr s2, =0xff000000
113 vldr d3, =0x0000fff000000001 define
115 vldr s4, =0xff000001
117 vldr d5, =0x0000fff000000001 define
119 vldr d6, =0x0000fff000000002 define
[all …]
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| D | neon-ldst-rm.d | 49 0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] ; 0[0-9a-f]+ <forward>
50 0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\]
51 0[0-9a-f]+ <[^>]+> ed135b01 vldr d5, \[r3, #-4\]
52 0[0-9a-f]+ <[^>]+> ed935b01 vldr d5, \[r3, #4\]
56 0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\]
57 0[0-9a-f]+ <[^>]+> ed135b40 vldr d5, \[r3, #-256\].*
58 0[0-9a-f]+ <[^>]+> ed935b40 vldr d5, \[r3, #256\].*
63 0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] ; 0[0-9a-f]+ <backward>
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| D | group-reloc-ldc.d | 392 0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].*
394 0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].*
396 0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].*
398 0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].*
400 0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].*
402 0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].*
416 0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].*
418 0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].*
420 0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].*
422 0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].*
[all …]
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| D | neon-ldst-rm.s | 34 vldr d22, forward
36 single vldr 4
38 single vldr 256
44 vldr d7, backward define
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| D | vldr.d | 3 # source: vldr.s
11 0[0-9a-f]+ <[^>]+> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000010 <float>
12 0[0-9a-f]+ <[^>]+> ed9f 0b02 vldr d0, \[pc, #8\] ; 00000010 <float>
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| D | vfp1.d | 27 0+044 <[^>]*> ed900b00 vldr d0, \[r0\]
112 0+198 <[^>]*> ed910b00 vldr d0, \[r1\]
113 0+19c <[^>]*> ed9e0b00 vldr d0, \[lr\]
114 0+1a0 <[^>]*> ed900b00 vldr d0, \[r0\]
115 0+1a4 <[^>]*> ed900bff vldr d0, \[r0, #1020\].*
116 0+1a8 <[^>]*> ed100bff vldr d0, \[r0, #-1020\].*
117 0+1ac <[^>]*> ed901b00 vldr d1, \[r0\]
118 0+1b0 <[^>]*> ed902b00 vldr d2, \[r0\]
119 0+1b4 <[^>]*> ed90fb00 vldr d15, \[r0\]
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| D | vldr.s | 4 vldr d0, float define
5 vldr d0, float define
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| D | ldr-global.d | 9 0+08 <[^>]*> ed9f0a02 ? vldr s0, \[pc, #8\] ; 0+18 <[^>]*>
12 0+10 <[^>]*> ed9f 0a01 ? vldr s0, \[pc, #4\] ; 0+18 <[^>]*>
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| D | ldr-global.s | 10 vldr s0, bar
15 vldr s0, bar
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| D | vfp1_t2.d | 27 0+044 <[^>]*> ed90 0b00 vldr d0, \[r0\]
112 0+198 <[^>]*> ed91 0b00 vldr d0, \[r1\]
113 0+19c <[^>]*> ed9e 0b00 vldr d0, \[lr\]
114 0+1a0 <[^>]*> ed90 0b00 vldr d0, \[r0\]
115 0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\].*
116 0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\].*
117 0+1ac <[^>]*> ed90 1b00 vldr d1, \[r0\]
118 0+1b0 <[^>]*> ed90 2b00 vldr d2, \[r0\]
119 0+1b4 <[^>]*> ed90 fb00 vldr d15, \[r0\]
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| D | vfp1xD.d | 28 0+048 <[^>]*> ed900a00 (vldr|flds) s0, \[r0\]
125 0+1cc <[^>]*> ed910a00 (vldr|flds) s0, \[r1\]
126 0+1d0 <[^>]*> ed9e0a00 (vldr|flds) s0, \[lr\]
127 0+1d4 <[^>]*> ed900a00 (vldr|flds) s0, \[r0\]
128 0+1d8 <[^>]*> ed900aff (vldr|flds) s0, \[r0, #1020\].*
129 0+1dc <[^>]*> ed100aff (vldr|flds) s0, \[r0, #-1020\].*
130 0+1e0 <[^>]*> edd00a00 (vldr|flds) s1, \[r0\]
131 0+1e4 <[^>]*> ed901a00 (vldr|flds) s2, \[r0\]
132 0+1e8 <[^>]*> edd0fa00 (vldr|flds) s31, \[r0\]
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| D | vfp1xD_t2.d | 28 0+048 <[^>]*> ed90 0a00 (vldr|flds) s0, \[r0\]
125 0+1cc <[^>]*> ed91 0a00 (vldr|flds) s0, \[r1\]
126 0+1d0 <[^>]*> ed9e 0a00 (vldr|flds) s0, \[lr\]
127 0+1d4 <[^>]*> ed90 0a00 (vldr|flds) s0, \[r0\]
128 0+1d8 <[^>]*> ed90 0aff (vldr|flds) s0, \[r0, #1020\].*
129 0+1dc <[^>]*> ed10 0aff (vldr|flds) s0, \[r0, #-1020\].*
130 0+1e0 <[^>]*> edd0 0a00 (vldr|flds) s1, \[r0\]
131 0+1e4 <[^>]*> ed90 1a00 (vldr|flds) s2, \[r0\]
132 0+1e8 <[^>]*> edd0 fa00 (vldr|flds) s31, \[r0\]
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| D | vfp-neon-overlap.d | 16 0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\]
17 0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\]
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| D | vfp-neon-syntax-inc.s | 160 single vldr
161 single vldr eq
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| D | vfpv3xd.d | 10 0+[0-9a-f]* <[^>]*> ed900b00 vldr d0, \[r0\]
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| D | group-reloc-ldc-encoding-bad.s | 153 vfp_test vldr vstr d0 0x1
154 vfp_test vldr vstr d0 0x808
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| D | group-reloc-ldc-parsing-bad.s | 54 ldctest2 vldr d0 FIXME
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| D | vfp-neon-syntax.d | 180 0[0-9a-f]+ <[^>]+> ed900a01 (vldr|flds) s0, \[r0, #4\]
181 0[0-9a-f]+ <[^>]+> ed900b01 (vldr|vldr) d0, \[r0, #4\]
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| D | vfp11-fix-scalar.d | 10 8004: ed927a00 (vldr|flds) s14, \[r2\]
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| D | vfp11-fix-vector.d | 11 8008: ed927a00 (vldr|flds) s14, \[r2\]
|