| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| D | addsub.d | 8 0: 0b0100f0 add w16, w7, w1
9 4: 0b2100f0 add w16, w7, w1, uxtb
10 8: 0b2100f0 add w16, w7, w1, uxtb
11 c: 0b2104f0 add w16, w7, w1, uxtb #1
12 10: 0b2108f0 add w16, w7, w1, uxtb #2
13 14: 0b210cf0 add w16, w7, w1, uxtb #3
14 18: 0b2110f0 add w16, w7, w1, uxtb #4
15 1c: 0b2120f0 add w16, w7, w1, uxth
16 20: 0b2120f0 add w16, w7, w1, uxth
17 24: 0b2124f0 add w16, w7, w1, uxth #1
[all …]
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| D | ldst-exclusive.d | 8 0: 080f7ce1 stxrb w15, w1, \[x7\]
9 4: 080f7ce1 stxrb w15, w1, \[x7\]
10 8: 080f7ce1 stxrb w15, w1, \[x7\]
11 c: 480f7ce1 stxrh w15, w1, \[x7\]
12 10: 480f7ce1 stxrh w15, w1, \[x7\]
13 14: 480f7ce1 stxrh w15, w1, \[x7\]
14 18: 880f7ce1 stxr w15, w1, \[x7\]
15 1c: 880f7ce1 stxr w15, w1, \[x7\]
16 20: 880f7ce1 stxr w15, w1, \[x7\]
20 30: 085f7ce1 ldxrb w1, \[x7\]
[all …]
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| D | int-insns.s | 12 extr w1, w2, w3, #31
17 subs w1,w1,#0
18 cmp w1,#0
20 neg w1,w2
21 sub w1,w2,#0
26 orr w1,wzr,#15
29 ldr w1, sp
30 ldr w1, =sp
45 subs w1,w1,#1
56 movz w1,#0x64
[all …]
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| D | alias.s | 25 extr w0, w1, w2, #15
32 madd w0, w1, w2, w3
33 madd w0, w1, w2, wzr
34 mul w0, w1, w2
38 smaddl x0, w1, w2, x3
39 smaddl x0, w1, w2, xzr
40 smull x0, w1, w2
41 smsubl x0, w1, w2, x3
42 smsubl x0, w1, w2, xzr
43 smnegl x0, w1, w2
[all …]
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| D | shifted.d | 36 70: 2a030041 orr w1, w2, w3
37 74: 2a030441 orr w1, w2, w3, lsl #1
38 78: 2a030c41 orr w1, w2, w3, lsl #3
39 7c: 2a031c41 orr w1, w2, w3, lsl #7
40 80: 2a033c41 orr w1, w2, w3, lsl #15
41 84: 2a037c41 orr w1, w2, w3, lsl #31
42 88: 2a430041 orr w1, w2, w3, lsr #0
43 8c: 2a430441 orr w1, w2, w3, lsr #1
44 90: 2a430c41 orr w1, w2, w3, lsr #3
45 94: 2a431c41 orr w1, w2, w3, lsr #7
[all …]
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| D | lse-atomic.d | 9 0: 88a07c41 cas w0, w1, \[x2\]
11 8: 88e07c41 casa w0, w1, \[x2\]
13 10: 88a0fc41 casl w0, w1, \[x2\]
15 18: 88e0fc41 casal w0, w1, \[x2\]
17 20: 08a07c41 casb w0, w1, \[x2\]
19 28: 48a07c41 cash w0, w1, \[x2\]
21 30: 08e07c41 casab w0, w1, \[x2\]
23 38: 08a0fc41 caslb w0, w1, \[x2\]
25 40: 08e0fc41 casalb w0, w1, \[x2\]
27 48: 48e07c41 casah w0, w1, \[x2\]
[all …]
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| D | alias.d | 8 0: 13823c20 extr w0, w1, w2, #15
14 18: 1b020c20 madd w0, w1, w2, w3
15 1c: 1b027c20 mul w0, w1, w2
16 20: 1b027c20 mul w0, w1, w2
20 30: 9b220c20 smaddl x0, w1, w2, x3
21 34: 9b227c20 smull x0, w1, w2
22 38: 9b227c20 smull x0, w1, w2
23 3c: 9b228c20 smsubl x0, w1, w2, x3
24 40: 9b22fc20 smnegl x0, w1, w2
25 44: 9b22fc20 smnegl x0, w1, w2
[all …]
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| D | no-aliases.d | 9 0: 13823c20 extr w0, w1, w2, #15
15 18: 1b020c20 madd w0, w1, w2, w3
16 1c: 1b027c20 madd w0, w1, w2, wzr
17 20: 1b027c20 madd w0, w1, w2, wzr
21 30: 9b220c20 smaddl x0, w1, w2, x3
22 34: 9b227c20 smaddl x0, w1, w2, xzr
23 38: 9b227c20 smaddl x0, w1, w2, xzr
24 3c: 9b228c20 smsubl x0, w1, w2, x3
25 40: 9b22fc20 smsubl x0, w1, w2, xzr
26 44: 9b22fc20 smsubl x0, w1, w2, xzr
[all …]
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| D | int-insns.d | 15 18: 13837c41 extr w1, w2, w3, #31
18 24: 71000021 subs w1, w1, #0x0
19 28: 7100003f cmp w1, #0x0
20 2c: 4b0203e1 neg w1, w2
21 30: 51000041 sub w1, w2, #0x0
24 3c: 32000fe1 orr w1, wzr, #0xf
26 44: 18000061 ldr w1, 50 <sp>
27 48: 18000621 ldr w1, 10c <sp\+0xbc>
39 70: 71000421 subs w1, w1, #0x1
49 98: 52800c81 mov w1, #0x64 // #100
[all …]
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| D | ldst-exclusive.s | 26 \op w1, [x7]
27 \op w1, [x7, #0]
28 \op w1, [x7, 0]
40 \op w15, w1, [x7]
41 \op w15, w1, [x7, #0]
42 \op w15, w1, [x7, 0]
54 \op w1, w2, [x7]
55 \op w1, w2, [x7, #0]
56 \op w1, w2, [x7, 0]
68 \op w15, w1, w2, [x7]
[all …]
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| D | shifted.s | 34 \op w1, w2, w3, \shift #0
35 \op w1, w2, w3, \shift #1
36 \op w1, w2, w3, \shift #3
37 \op w1, w2, w3, \shift #7
38 \op w1, w2, w3, \shift #15
39 \op w1, w2, w3, \shift #31
59 \op w1, w2, w3, \shift
60 \op w1, w2, w3, \shift #1
61 \op w1, w2, w3, \shift #2
62 \op w1, w2, w3, \shift #3
[all …]
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| D | rm-simd-ext.s | 25 add w1, w1, w3
28 orr w1, w1, w3
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| D | symbol.d | 8 0: b9400401 ldr w1, \[x0,#4\]
9 4: b9400401 ldr w1, \[x0,#4\]
10 8: b9401001 ldr w1, \[x0,#16\]
11 c: b9401001 ldr w1, \[x0,#16\]
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| D | symbol.s | 14 ldr w1, [x0, #$CPU_mode]
15 ldr w1, [x0, $CPU_mode]
16 ldr w1, [x0, #CPU_mode]
17 ldr w1, [x0, CPU_mode]
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| D | illegal.s | 48 bfm w0, w1, 8, 43
73 stxrb x2, w1, [sp]
97 smaddl w0, w1, w2, x3
99 smaddl x0, w1, x2, x3
100 smaddl x0, w1, w2, w3
205 movz w1,#:abs_g2:u48
206 movz w1,#:abs_g3:u48
232 fmov w0, w1
459 \instr d0, w1, 33
465 \instr w1, d0, 33
[all …]
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| D | msa-branch.s | 4 fsune.d $w0,$w1,$w2
6 fsune.d $w0,$w1,$w2
7 bz.b $w1, test
8 fsune.d $w0,$w1,$w2
13 bz.b $w1, test
19 bz.b $w1, test
23 fsune.d $w0,$w1,$w2
25 fsune.d $w0,$w1,$w2
26 bz.h $w1, test
27 fsune.d $w0,$w1,$w2
[all …]
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| D | msa-branch.d | 8 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
11 [0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <test>
12 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
14 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
18 [0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <test>
25 [0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <test>
29 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
32 [0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ <test>
33 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
35 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
[all …]
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| D | mipsr6@msa-branch.d | 9 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
13 [0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <[^>]*>
15 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
18 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
23 [0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <[^>]*>
33 [0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <[^>]*>
39 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
43 [0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ <[^>]*>
45 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
48 [0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
[all …]
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| D | micromips@msa-branch.d | 9 [0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
13 [0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*>
15 [0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
18 [0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
23 [0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*>
33 [0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*>
39 [0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
43 [0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*>
45 [0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
48 [0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
[all …]
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| D | msa.s | 6 sll.b $w0,$w1,$w2
19 sra.h $w31,$w0,$w1
33 srl.d $w1,$w2,$w3
46 bclri.b $w0,$w1,0
60 bseti.h $w0,$w1,0
74 bnegi.w $w0,$w1,0
88 binsli.d $w0,$w1,0
102 addv.b $w0,$w1,$w2
115 subv.h $w31,$w0,$w1
129 max_s.d $w1,$w2,$w3
[all …]
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| D | elf-rel2.s | 3 .type w1,@object
4 .size w1,4
5 w1: .word 1 label
27 lw $2,w1
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
| D | tls-relax-all.s | 24 ldr w1, [x0]
33 add w1, w1, w0
39 add w1, w1, w0
45 add w1, w1, w0
51 add w0, w1, w0
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| D | tls-relax-all.d | 13 +10020: b9400001 ldr w1, \[x0\]
21 +10040: 0b000021 add w1, w1, w0
27 +10058: 0b000021 add w1, w1, w0
33 +10070: 0b000021 add w1, w1, w0
39 +10088: 0b000020 add w0, w1, w0
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic6x/ |
| D | insns-c674x-reloc.s | 3 w1: label
20 addab .D1X b14,w2-w1,a15
26 addah .D1X b14,w2-w1,a15
32 addaw .D1X b14,w2-w1,a15
38 addk .S1 w2-w1,a4
42 mvk .S1 w2-w1,a4
66 ldb .D2T2 *+b14(w2-w1),b1
72 ldbu .D2T2 *+b14(w2-w1),b1
78 ldh .D2T2 *+b14(w2-w1),b1
84 ldhu .D2T2 *+b14(w2-w1),b1
[all …]
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| /toolchain/binutils/binutils-2.25/include/ |
| D | longlong.h | 326 #define umul_ppmm(w1, w0, u, v) \ argument
330 (w1) = (USItype) (__x >> 32); \
360 #define umul_ppmm(w1, w0, u, v) \ argument
371 (w1) = __t.__w1w0.__w1; \
467 #define umul_ppmm(w1, w0, u, v) \ argument
470 "=d" ((USItype) (w1)) \
503 #define umul_ppmm(w1, w0, u, v) \ argument
506 "=d" ((UDItype) (w1)) \
523 #define umul_ppmm(w1, w0, u, v) \ argument
531 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
[all …]
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