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Searched refs:R11 (Results 1 – 11 of 11) sorted by relevance

/art/runtime/arch/x86_64/
Dregisters_x86_64.h41 R11 = 11, enumerator
Dcontext_x86_64.cc73 gprs_[R11] = nullptr; in SmashCallerSaves()
/art/runtime/arch/arm/
Dregisters_arm.h38 R11 = 11, enumerator
Dquick_method_frame_info_arm.h32 (1 << art::arm::R10) | (1 << art::arm::R11);
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc232 callee_save_regs_.push_back(ArmManagedRegister::FromCoreRegister(R11)); in ArmJniCallingConvention()
242 result = 1 << R5 | 1 << R6 | 1 << R7 | 1 << R8 | 1 << R10 | 1 << R11 | 1 << LR; in CoreSpillMask()
/art/compiler/utils/arm/
Dassembler_arm32_test.cc74 new arm::Register(arm::R11), in SetUpHelpers()
94 new arm::Register(arm::R11), in SetUpHelpers()
156 shifter_operands_.push_back(arm::ShifterOperand(arm::R11)); in SetUpHelpers()
164 shifter_operands_.push_back(arm::ShifterOperand(arm::R11)); in SetUpHelpers()
Dassembler_thumb2_test.cc60 new arm::Register(arm::R11), in SetUpHelpers()
337 __ StoreToOffset(type, arm::R11, arm::SP, offset); in TEST_F()
338 __ StoreToOffset(type, arm::R11, arm::R5, offset); in TEST_F()
356 __ StoreToOffset(type, arm::R11, arm::SP, offset); in TEST_F()
357 __ StoreToOffset(type, arm::R11, arm::R5, offset); in TEST_F()
/art/compiler/utils/
Dassembler_thumb_test.cc779 __ ldm(DB_W, R4, (1 << LR | 1 << R11)); in TEST_F()
780 __ ldm(DB, R4, (1 << LR | 1 << R11)); in TEST_F()
793 __ stm(IA_W, R4, (1 << LR | 1 << R11)); in TEST_F()
794 __ stm(IA, R4, (1 << LR | 1 << R11)); in TEST_F()
958 __ umull(R8, R9, R10, R11); in TEST_F()
1291 __ CompareAndBranchIfZero(arm::R11, &label); in TEST_F()
1293 __ CompareAndBranchIfNonZero(arm::R11, &label); in TEST_F()
/art/compiler/utils/x86_64/
Dassembler_x86_64_test.cc156 registers_.push_back(new x86_64::CpuRegister(x86_64::R11)); in SetUpHelpers()
173 secondary_register_names_.emplace(x86_64::CpuRegister(x86_64::R11), "r11d"); in SetUpHelpers()
190 tertiary_register_names_.emplace(x86_64::CpuRegister(x86_64::R11), "r11w"); in SetUpHelpers()
207 quaternary_register_names_.emplace(x86_64::CpuRegister(x86_64::R11), "r11b"); in SetUpHelpers()
/art/compiler/optimizing/
Dcode_generator_x86_64.h35 static constexpr Register TMP = R11;
Dcode_generator_arm.cc52 { R5, R6, R7, R8, R10, R11, LR };