| /external/e2fsprogs/lib/ext2fs/ |
| D | bitops.c | 36 unsigned char *ADDR = (unsigned char *) addr; in ext2fs_set_bit() local
38 ADDR += nr >> 3; in ext2fs_set_bit()
40 retval = mask & *ADDR; in ext2fs_set_bit()
41 *ADDR |= mask; in ext2fs_set_bit()
48 unsigned char *ADDR = (unsigned char *) addr; in ext2fs_clear_bit() local
50 ADDR += nr >> 3; in ext2fs_clear_bit()
52 retval = mask & *ADDR; in ext2fs_clear_bit()
53 *ADDR &= ~mask; in ext2fs_clear_bit()
60 const unsigned char *ADDR = (const unsigned char *) addr; in ext2fs_test_bit() local
62 ADDR += nr >> 3; in ext2fs_test_bit()
[all …]
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| D | bitops.h | 244 unsigned char *ADDR = (unsigned char *) addr; in ext2fs_fast_set_bit() local
246 ADDR += nr >> 3; in ext2fs_fast_set_bit()
247 *ADDR |= (unsigned char) (1 << (nr & 0x07)); in ext2fs_fast_set_bit()
252 unsigned char *ADDR = (unsigned char *) addr; in ext2fs_fast_clear_bit() local
254 ADDR += nr >> 3; in ext2fs_fast_clear_bit()
255 *ADDR &= (unsigned char) ~(1 << (nr & 0x07)); in ext2fs_fast_clear_bit()
261 unsigned char *ADDR = (unsigned char *) addr; in ext2fs_fast_set_bit64() local
263 ADDR += nr >> 3; in ext2fs_fast_set_bit64()
264 *ADDR |= (unsigned char) (1 << (nr & 0x07)); in ext2fs_fast_set_bit64()
269 unsigned char *ADDR = (unsigned char *) addr; in ext2fs_fast_clear_bit64() local
[all …]
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| /external/llvm/test/CodeGen/ARM/ |
| D | atomic-ops-v8.ll | 16 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
17 ; CHECK: movt r[[ADDR]], :upper16:var8
20 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
24 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
39 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
40 ; CHECK: movt r[[ADDR]], :upper16:var16
43 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
47 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
62 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
63 ; CHECK: movt r[[ADDR]], :upper16:var32
[all …]
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| D | 2010-05-18-PostIndexBug.ll | 10 ; ARM-DAG: mov r[[ADDR:[0-9]+]], #8
12 ; ARM: str [[VAL]], [r[[ADDR]]], r0
15 ; THUMB-DAG: movs r[[ADDR:[0-9]+]], #8
18 ; THUMB: str [[VAL]], [r[[ADDR]]]
|
| D | ldstrex.ll | 120 ; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024
121 ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
122 ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
130 ; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1
131 ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
132 ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
138 ; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
139 ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
140 ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
|
| /external/llvm/test/tools/llvm-symbolizer/pdb/ |
| D | pdb.test | 1 RUN: grep '^ADDR:' %s | sed -s 's/ADDR: //' \
4 RUN: grep '^ADDR:' %s | sed -s 's/ADDR: //' \
11 RUN: grep '^ADDR:' %s | sed -s 's/ADDR: //' \
16 ADDR: 0x401000
17 ADDR: 0x401010
18 ADDR: 0x401070
19 ADDR: 0x401030
20 ADDR: 0x401040
21 ADDR: 0x401050
22 ADDR: 0x401060
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | atomic-ops.ll | 20 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
23 ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
27 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
40 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
43 ; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
47 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
60 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
63 ; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
67 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
80 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
[all …]
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| D | arm64-atomic.ll | 5 ; CHECK-NEXT: mov x[[ADDR:[0-9]+]], x0
7 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
10 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
42 ; CHECK-NEXT: mov x[[ADDR:[0-9]+]], x0
44 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]
47 ; CHECK-NEXT: stlxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]
60 ; CHECK-NEXT: mov x[[ADDR:[0-9]+]], x0
62 ; CHECK-NEXT: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
65 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
92 ; CHECK: mov x[[ADDR:[0-9]+]], x0
[all …]
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| D | arm64-2012-05-07-MemcpyAlignBug.ll | 10 ; CHECK: add x[[ADDR:[0-9]+]], x[[PAGE]], {{l_b@PAGEOFF|:lo12:.Lb}}
11 ; CHECK-NEXT: ldr [[VAL:w[0-9]+]], [x[[ADDR]], #8]
13 ; CHECK-NEXT: ldr [[VAL2:x[0-9]+]], [x[[ADDR]]]
|
| D | extern-weak.ll | 50 ; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g3:arr_var
51 ; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var
52 ; CHECK-LARGE: movk [[ADDR]], #:abs_g1_nc:arr_var
53 ; CHECK-LARGE: movk [[ADDR]], #:abs_g0_nc:arr_var
|
| D | global-alignment.ll | 16 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:var32
17 ; CHECK: ldr x0, [x[[ADDR]]]
73 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:yet_another_var
74 ; CHECK: ldr x0, [x[[ADDR]]]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | alloca-02.ll | 13 ; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
14 ; CHECK-A: la %r2, 160([[ADDR]])
18 ; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
19 ; CHECK-B: la %r2, 160([[ADDR]])
23 ; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
24 ; CHECK-C-DAG: la %r2, 160([[ADDR]])
29 ; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
30 ; CHECK-D-DAG: la %r2, 160([[ADDR]])
35 ; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
36 ; CHECK-E-DAG: la %r2, 160([[ADDR]])
|
| /external/llvm/test/tools/llvm-symbolizer/ |
| D | coff-exports.test | 1 RUN: grep '^ADDR:' %s | sed -s 's/ADDR: //' \
8 ADDR: 0x500A
9 ADDR: 0x5038
10 ADDR: 0x504B
|
| D | coff-dwarf.test | 1 RUN: grep '^ADDR:' %s | sed -s 's/ADDR: //' \
8 ADDR: 0x5009
9 ADDR: 0x5038
|
| /external/libunwind/tests/ |
| D | flush-cache.h | 31 #define flush_cache(ADDR, LEN) \ argument
32 __builtin___clear_cache((ADDR), (ADDR) + (LEN))
|
| /external/mesa3d/src/gallium/tests/graw/vertex-shader/ |
| D | vert-arr.sh | 9 DCL ADDR[0]
20 ARR ADDR[0].x, TEMP[0]
21 MOV OUT[1], IMM[ADDR[0].x + 3]
|
| D | vert-arl.sh | 9 DCL ADDR[0]
20 ARL ADDR[0].x, TEMP[0]
21 MOV OUT[1], IMM[ADDR[0].x + 3]
|
| D | vert-flr.sh | 9 DCL ADDR[0]
20 FLR ADDR[0].x, TEMP[0]
21 MOV OUT[1], IMM[ADDR[0].x + 3]
|
| /external/libvncserver/examples/ |
| D | zippy.c | 106 #define ADDR(x,y) s->frameBuffer+(x)*bpp+(y)*s->paddedWidthInBytes in draw_primary_colours_generic_fast() macro
107 memcpy(ADDR(i,j+y1),ADDR(x1,y1),bpp); in draw_primary_colours_generic_fast()
108 memcpy(ADDR(i,j+y3),ADDR(x1,y3),bpp); in draw_primary_colours_generic_fast()
109 memcpy(ADDR(i,j+y4),ADDR(x1,y4),bpp); in draw_primary_colours_generic_fast()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | EvergreenInstructions.td | 626 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
627 "TEX $COUNT @$ADDR"> {
630 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
631 "VTX $COUNT @$ADDR"> {
634 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
635 "LOOP_START_DX10 @$ADDR"> {
639 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
643 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
644 "LOOP_BREAK @$ADDR"> {
648 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
[all …]
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| /external/llvm/test/Transforms/CrossDSOCFI/ |
| D | basic.ll | 3 ; CHECK: define void @__cfi_check(i64 %[[TYPE:.*]], i8* %[[ADDR:.*]]) align 4096
19 ; CHECK-NEXT: call i1 @llvm.bitset.test(i8* %[[ADDR]], metadata i64 111)
23 ; CHECK-NEXT: call i1 @llvm.bitset.test(i8* %[[ADDR]], metadata i64 222)
27 ; CHECK-NEXT: call i1 @llvm.bitset.test(i8* %[[ADDR]], metadata i64 333)
31 ; CHECK-NEXT: call i1 @llvm.bitset.test(i8* %[[ADDR]], metadata i64 444)
|
| /external/f2fs-tools/lib/ |
| D | libf2fs.c | 81 unsigned char *ADDR = (unsigned char *) addr; in set_bit() local
83 ADDR += nr >> 3; in set_bit()
85 retval = mask & *ADDR; in set_bit()
86 *ADDR |= mask; in set_bit()
93 unsigned char *ADDR = (unsigned char *) addr; in clear_bit() local
95 ADDR += nr >> 3; in clear_bit()
97 retval = mask & *ADDR; in clear_bit()
98 *ADDR &= ~mask; in clear_bit()
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | 2013-03-02-vduplane-nonconstant-source-index.ll | 4 ; CHECK: lsls r[[ADDR:[0-9]+]], r[[ADDR]], #2
5 ; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128], r[[ADDR]]
|
| /external/llvm/test/CodeGen/X86/ |
| D | x32-va_start.ll | 60 ; CHECK: movl {{[^,]*}}, [[ADDR:.*]]
61 ; CHECK: addl [[COUNT]], [[ADDR]]
63 ; NOSSE: movl ([[ADDR]]), %eax
72 ; CHECK: movl {{[^,]*}}, [[ADDR]]
73 ; NOSSE: movl ([[ADDR]]), %eax
84 ; SSE: movl ([[ADDR]]), %eax
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | sext-in-reg.ll | 14 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
15 ; EG: LSHR * [[ADDR]]
30 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
33 ; EG-NEXT: LSHR * [[ADDR]]
48 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
51 ; EG-NEXT: LSHR * [[ADDR]]
66 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
69 ; EG-NEXT: LSHR * [[ADDR]]
270 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
275 ; EG: LSHR {{\*?}} [[ADDR]]
[all …]
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