| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV5.td | 84 [(set F64:$dst, fpimm:$src1)]>,
146 defm: Storex_pat<store, F64, s29_3ImmPred, S2_storerd_io>;
148 def: Storex_simple_pat<store, F64, S2_storerd_io>;
260 [(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
292 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
293 (DoubleMI F64:$src1, F64:$src2)>;
311 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
312 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
313 (DoubleMI F64:$src1, F64:$src2))>;
341 def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
[all …]
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| D | HexagonIntrinsics.td | 121 : Pat<(IntID (F64:$Rs)),
122 (MI (F64:$Rs))>;
126 : Pat<(IntID F64:$Rs, ImmPred:$It),
127 (MI F64:$Rs, ImmPred:$It)>;
143 : Pat<(IntID F64:$Rs, F64:$Rt),
144 (MI F64:$Rs, F64:$Rt)>;
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrConv.td | 52 def I32_TRUNC_S_F64 : I<(outs I32:$dst), (ins F64:$src),
53 [(set I32:$dst, (fp_to_sint F64:$src))],
55 def I32_TRUNC_U_F64 : I<(outs I32:$dst), (ins F64:$src),
56 [(set I32:$dst, (fp_to_uint F64:$src))],
58 def I64_TRUNC_S_F64 : I<(outs I64:$dst), (ins F64:$src),
59 [(set I64:$dst, (fp_to_sint F64:$src))],
61 def I64_TRUNC_U_F64 : I<(outs I64:$dst), (ins F64:$src),
62 [(set I64:$dst, (fp_to_uint F64:$src))],
72 def F64_CONVERT_S_I32 : I<(outs F64:$dst), (ins I32:$src),
73 [(set F64:$dst, (sint_to_fp I32:$src))],
[all …]
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| D | WebAssemblyInstrFloat.td | 42 def : Pat<(fcopysign F64:$lhs, F32:$rhs),
43 (COPYSIGN_F64 F64:$lhs, (F64_PROMOTE_F32 F32:$rhs))>;
44 def : Pat<(fcopysign F32:$lhs, F64:$rhs),
45 (COPYSIGN_F32 F32:$lhs, (F32_DEMOTE_F64 F64:$rhs))>;
83 def SELECT_F64 : I<(outs F64:$dst), (ins I32:$cond, F64:$lhs, F64:$rhs),
84 [(set F64:$dst, (select I32:$cond, F64:$lhs, F64:$rhs))],
94 def : Pat<(select (i32 (setne I32:$cond, 0)), F64:$lhs, F64:$rhs),
95 (SELECT_F64 I32:$cond, F64:$lhs, F64:$rhs)>;
100 def : Pat<(select (i32 (seteq I32:$cond, 0)), F64:$lhs, F64:$rhs),
101 (SELECT_F64 I32:$cond, F64:$rhs, F64:$lhs)>;
|
| D | WebAssemblyInstrFormats.td | 52 def _F64 : I<(outs F64:$dst), (ins F64:$src),
53 [(set F64:$dst, (node F64:$src))],
60 def _F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs),
61 [(set F64:$dst, (node F64:$lhs, F64:$rhs))],
76 def _F64 : I<(outs I32:$dst), (ins F64:$lhs, F64:$rhs),
77 [(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],
|
| D | WebAssemblyInstrInfo.td | 89 defm : ARGUMENT<F64>;
114 defm : LOCAL<F64>;
126 def CONST_F64 : I<(outs F64:$res), (ins f64imm:$imm),
127 [(set F64:$res, fpimm:$imm)],
|
| D | WebAssemblyInstrMemory.td | 40 def LOAD_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr), [],
334 def STORE_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr, F64:$val), [],
343 def : Pat<(store F64:$val, I32:$addr), (STORE_F64 0, I32:$addr, F64:$val)>;
352 def : Pat<(store F64:$val, (regPlusImm imm:$off, I32:$addr)),
353 (STORE_F64 imm:$off, I32:$addr, F64:$val)>;
360 def : Pat<(store F64:$val, (regPlusImm tglobaladdr:$off, I32:$addr)),
361 (STORE_F64 tglobaladdr:$off, I32:$addr, F64:$val)>;
368 def : Pat<(store F64:$val, (regPlusImm texternalsym:$off, I32:$addr)),
369 (STORE_F64 texternalsym:$off, I32:$addr, F64:$val)>;
378 def : Pat<(store F64:$val, imm:$off),
[all …]
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| D | WebAssemblyRegisterInfo.td | 58 def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
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| D | WebAssemblyInstrCall.td | 40 defm : CALL<F64, "f64.">;
|
| D | WebAssemblyInstrControl.td | 72 defm : RETURN<F64>;
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 2791 enum VFPType { S32, U32, F32, F64 }; enumerator
2813 case F64: in IsIntegerVFPType()
2826 case F64: in IsDoubleVFPType()
2906 emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond)); in vcvt_f64_s32()
2922 emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond)); in vcvt_f64_u32()
2930 emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond)); in vcvt_s32_f64()
2938 emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond)); in vcvt_u32_f64()
2946 emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond)); in vcvt_f64_f32()
2954 emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond)); in vcvt_f32_f64()
|
| /external/valgrind/docs/internals/ |
| D | register-uses.txt | 132 holding the address for F32/F64 spills, since the VFP load/store
|
| /external/icu/icu4c/source/data/sprep/ |
| D | rfc3722.txt | 1079 1F6C; 1F64; MAP
1119 1FA4; 1F64 03B9; MAP
1127 1FAC; 1F64 03B9; MAP
|
| D | rfc3920node.txt | 1079 1F6C; 1F64; MAP
1119 1FA4; 1F64 03B9; MAP
1127 1FAC; 1F64 03B9; MAP
|
| D | rfc4518ci.txt | 1046 1F6C; 1F64; MAP
1086 1FA4; 1F64 03B9; MAP
1094 1FAC; 1F64 03B9; MAP
|
| D | rfc3530csci.txt | 1078 1F6C; 1F64; MAP
1118 1FA4; 1F64 03B9; MAP
1126 1FAC; 1F64 03B9; MAP
|
| D | rfc3491.txt | 1079 1F6C; 1F64; MAP
1119 1FA4; 1F64 03B9; MAP
1127 1FAC; 1F64 03B9; MAP
|
| /external/icu/icu4c/source/test/testdata/ |
| D | nfs4_cs_prep_ci.txt | 1069 1F6C; 1F64; MAP
1109 1FA4; 1F64 03B9; MAP
1117 1FAC; 1F64 03B9; MAP
|
| D | nfs4_cis_prep.txt | 1069 1F6C; 1F64; MAP
1109 1FA4; 1F64 03B9; MAP
1117 1FAC; 1F64 03B9; MAP
|
| D | nfs4_mixed_prep_s.txt | 1069 1F6C; 1F64; MAP
1109 1FA4; 1F64 03B9; MAP
1117 1FAC; 1F64 03B9; MAP
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 447 // ASIMD FP divide, Q-form, F64
455 // ASIMD FP square root, Q-form, F64
|
| /external/valgrind/VEX/priv/ |
| D | ir_defs.c | 85 case Ico_F64: u.f64 = con->Ico.F64; in ppIRConst()
1730 c->Ico.F64 = f64; in IRConst_F64()
2256 case Ico_F64: return IRConst_F64(c->Ico.F64); in deepCopyIRConst()
4616 case Ico_F64: return toBool( c1->Ico.F64 == c2->Ico.F64 ); in eqIRConst()
|
| /external/icu/icu4c/source/data/unidata/norm2/ |
| D | nfc.txt | 1084 1F64=1F60 0301
1146 1FA4=1F64 0345
|
| D | nfkc_cf.txt | 911 1F6C>1F64
958 1FA4>1F64 03B9
966 1FAC>1F64 03B9
1555 2F64>7528
|
| /external/valgrind/VEX/pub/ |
| D | libvex_ir.h | 302 Double F64; member
|