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Searched refs:FP_TO_SINT (Results 1 – 25 of 37) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp127 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
129 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
131 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
145 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
147 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
149 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
162 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
164 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
166 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
168 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
DARMISelLowering.cpp106 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
111 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
572 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
625 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
677 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
679 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
3914 if (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
6454 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
6494 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6606 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp256 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
257 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
258 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
264 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
266 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
272 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
278 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
279 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
DAArch64ISelLowering.cpp173 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
174 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
175 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in AArch64TargetLowering()
484 setTargetDAGCombine(ISD::FP_TO_SINT); in AArch64TargetLowering()
556 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
691 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom); in addTypeForNEON()
1902 if (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
2329 case ISD::FP_TO_SINT: in LowerOperation()
7612 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; in performFpToIntCombine()
9615 case ISD::FP_TO_SINT: in PerformDAGCombine()
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/external/llvm/test/CodeGen/X86/
Davx-fp2int.ll3 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
Dhalf.ll119 ; FP_TO_UINT is expanded using FP_TO_SINT
/external/llvm/test/CodeGen/AMDGPU/
Dfcmp.ll19 ; SET* + FP_TO_SINT
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h593 ISD::FP_TO_SINT, 0),
595 ISD::FP_TO_SINT, 0),
597 ISD::FP_TO_SINT, ISD::FP_TO_SINT),
599 ISD::FP_TO_SINT, 0),
601 ISD::FP_TO_SINT, 0),
603 ISD::FP_TO_SINT, ISD::FP_TO_SINT),
617 ISD::FP_TO_SINT, 0),
619 ISD::FP_TO_SINT, 0),
621 ISD::FP_TO_SINT, ISD::FP_TO_SINT),
623 ISD::FP_TO_SINT, 0),
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DREADME-FPStack.txt50 FP_TO_SINT when the source operand is already in memory.
DX86TargetTransformInfo.cpp700 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, in getCastInstrCost()
701 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, in getCastInstrCost()
DX86InstrFragmentsSIMD.td534 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
536 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp298 case ISD::FP_TO_SINT: in LegalizeOp()
392 case ISD::FP_TO_SINT: in Promote()
394 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT); in Promote()
478 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { in PromoteFP_TO_INT()
479 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
DLegalizeFloatTypes.cpp742 case ISD::FP_TO_SINT: in SoftenFloatOperand()
869 bool Signed = N->getOpcode() == ISD::FP_TO_SINT; in SoftenFloatOp_FP_TO_XINT()
1491 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break; in ExpandFloatOperand()
1598 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in ExpandFloatOp_FP_TO_SINT()
1623 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, in ExpandFloatOp_FP_TO_UINT()
1630 DAG.getNode(ISD::FP_TO_SINT, dl, in ExpandFloatOp_FP_TO_UINT()
1729 case ISD::FP_TO_SINT: in PromoteFloatOperand()
DSelectionDAGDumper.cpp255 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
DLegalizeVectorTypes.cpp89 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
440 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
645 case ISD::FP_TO_SINT: in SplitVectorResult()
1427 case ISD::FP_TO_SINT: in SplitVectorOperand()
2075 case ISD::FP_TO_SINT: in WidenVectorResult()
2979 case ISD::FP_TO_SINT: in WidenVectorOperand()
DLegalizeDAG.cpp2788 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { in PromoteLegalFP_TO_INT()
2789 OpToUse = ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
3151 case ISD::FP_TO_SINT: in ExpandNode()
3167 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); in ExpandNode()
3169 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, in ExpandNode()
4267 case ISD::FP_TO_SINT: in PromoteNode()
4269 Node->getOpcode() == ISD::FP_TO_SINT, dl); in PromoteNode()
DLegalizeIntegerTypes.cpp109 case ISD::FP_TO_SINT: in PromoteIntegerResult()
422 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
423 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
1317 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; in ExpandIntegerResult()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h445 FP_TO_SINT, enumerator
/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp417 ConversionOp = ISD::FP_TO_SINT; in LowerSELECT_CC()
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32, in LowerSELECT_CC()
DAMDILISelLowering.cpp545 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq); in LowerSDIV24()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp252 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
362 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
380 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
386 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
509 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
640 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
686 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal); in PPCTargetLowering()
736 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal); in PPCTargetLowering()
6127 Op.getOpcode() == ISD::FP_TO_SINT in LowerFP_TO_INTForReuse()
6133 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) && in LowerFP_TO_INTForReuse()
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/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
169 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
881 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1855 case ISD::FP_TO_SINT: { in PerformDAGCombine()
DAMDGPUISelLowering.cpp276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
299 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in AMDGPUTargetLowering()
634 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
1555 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2241 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1836 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1837 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1838 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
1851 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); in HexagonTargetLowering()
1852 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); in HexagonTargetLowering()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1523 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1525 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
2934 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3330 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3336 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()

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