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Searched refs:GPRC (Results 1 – 6 of 6) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp355 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
356 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
405 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
413 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
475 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
477 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
489 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
520 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
522 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
534 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
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DPPCRegisterInfo.td233 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
238 let AltOrders = [(add (sub GPRC, R2), R2)];
260 def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)> {
DPPCFrameLowering.cpp1527 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in addScavengingSpillSlot() local
1529 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
DPPCInstrInfo.td393 def gprc : RegisterOperand<GPRC> {
/external/llvm/test/CodeGen/PowerPC/
Dasym-regclass-copy.ll5 ; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with
6 ; GPRC is handled correctly. When it was not, this test would assert.
/external/llvm/docs/
DCodeGenerator.rst1067 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
1071 def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
1072 (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;