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/external/mesa3d/src/gallium/tests/graw/vertex-shader/
Dvert-arr.sh11 IMM FLT32 { 3.0, 1.0, 1.0, 1.0 }
12 IMM FLT32 { 1.0, 0.0, 0.0, 1.0 }
13 IMM FLT32 { 0.0, 1.0, 0.0, 1.0 }
14 IMM FLT32 { 0.0, 0.0, 1.0, 1.0 }
15 IMM FLT32 { 1.0, 1.0, 0.0, 1.0 }
16 IMM FLT32 { 0.0, 1.0, 1.0, 1.0 }
19 MUL TEMP[0], IN[0], IMM[0]
21 MOV OUT[1], IMM[ADDR[0].x + 3]
Dvert-arl.sh11 IMM FLT32 { 3.0, 1.0, 1.0, 1.0 }
12 IMM FLT32 { 1.0, 0.0, 0.0, 1.0 }
13 IMM FLT32 { 0.0, 1.0, 0.0, 1.0 }
14 IMM FLT32 { 0.0, 0.0, 1.0, 1.0 }
15 IMM FLT32 { 1.0, 1.0, 0.0, 1.0 }
16 IMM FLT32 { 0.0, 1.0, 1.0, 1.0 }
19 MUL TEMP[0], IN[0], IMM[0]
21 MOV OUT[1], IMM[ADDR[0].x + 3]
Dvert-flr.sh11 IMM FLT32 { 3.0, 1.0, 1.0, 1.0 }
12 IMM FLT32 { 1.0, 0.0, 0.0, 1.0 }
13 IMM FLT32 { 0.0, 1.0, 0.0, 1.0 }
14 IMM FLT32 { 0.0, 0.0, 1.0, 1.0 }
15 IMM FLT32 { 1.0, 1.0, 0.0, 1.0 }
16 IMM FLT32 { 0.0, 1.0, 1.0, 1.0 }
19 MUL TEMP[0], IN[0], IMM[0]
21 MOV OUT[1], IMM[ADDR[0].x + 3]
Dvert-mad.sh8 IMM FLT32 { 0.5, 1.0, 1.0, 1.0 }
9 IMM FLT32 { 0.5, 0.0, 0.0, 0.0 }
11 MAD OUT[0], IN[0], IMM[0], IMM[1]
Dvert-lg2.sh10 IMM FLT32 { 1.0, 0.0, 0.0, 0.0 }
11 IMM FLT32 { 0.5, 0.0, 0.0, 0.0 }
13 ADD TEMP[0], IN[0], IMM[0]
15 ADD OUT[0], TEMP[0], IMM[1]
Dvert-rcp.sh10 IMM FLT32 { 1.0, 0.0, 0.0, 0.0 }
11 IMM FLT32 { 1.5, 0.0, 0.0, 0.0 }
13 ADD TEMP[0], IN[0], IMM[0]
15 SUB OUT[0], TEMP[0], IMM[1]
Dvert-rsq.sh10 IMM FLT32 { 1.0, 0.0, 0.0, 0.0 }
11 IMM FLT32 { 1.5, 0.0, 0.0, 0.0 }
13 ADD TEMP[0], IN[0], IMM[0]
15 SUB OUT[0], TEMP[0], IMM[1]
/external/mesa3d/src/gallium/tests/python/tests/regress/fragment-shader/
Dfrag-cmp.sh6 IMM FLT32 { 1, 0, 0, 1 }
7 IMM FLT32 { 0, 1, 1, 0 }
8 IMM FLT32 { 1, 0,-1, 0 }
10 CMP OUT[0], IMM[2], IMM[0], IMM[1]
/external/mesa3d/src/gallium/tests/graw/fragment-shader/
Dfrag-kil.sh8 IMM FLT32 { 0.6, 0.6, 0.6, 0.0 }
9 IMM FLT32 { 0.01, 0.0, 0.0, 0.0 }
10 IMM FLT32 { 1.0, 0.0, 0.0, 0.0 }
12 SLT TEMP[0], IN[0], IMM[0]
14 MOV OUT[0].w, IMM[2].xxxx
15 SUB TEMP[0], TEMP[0], IMM[1].xxxy
Dfrag-mad.sh6 IMM FLT32 { 0.5, 0.4, 0.6, 1.0 }
7 IMM FLT32 { 0.5, 0.4, 0.6, 0.0 }
9 MAD OUT[0], IN[0], IMM[0], IMM[1]
Dfrag-srcmod-absneg.sh8 IMM FLT32 { -0.2, -0.3, -0.4, 0.0 }
9 IMM FLT32 { -1.0, -1.0, -1.0, -1.0 }
11 ADD TEMP[0], IN[0], IMM[0]
13 MUL OUT[0], TEMP[0], IMM[1]
Dfrag-flr.sh8 IMM FLT32 { 2.5, 4.0, 2.0, 1.0 }
9 IMM FLT32 { 0.4, 0.25, 0.5, 1.0 }
11 MUL TEMP[0], IN[0], IMM[0]
13 MUL OUT[0], TEMP[0], IMM[1]
Dfrag-lg2.sh8 IMM FLT32 { 1.0, 0.0, 0.0, 0.0 }
9 IMM FLT32 { 0.5, 0.0, 0.0, 0.0 }
11 ADD TEMP[0], IN[0], IMM[0]
13 ADD OUT[0], TEMP[0], IMM[1]
Dfrag-rsq.sh8 IMM FLT32 { 1.0, 0.0, 0.0, 0.0 }
9 IMM FLT32 { 1.5, 0.0, 0.0, 0.0 }
11 ADD TEMP[0], IN[0], IMM[0]
13 SUB OUT[0], TEMP[0], IMM[1]
Dfrag-rcp.sh8 IMM FLT32 { 1.0, 0.0, 0.0, 0.0 }
9 IMM FLT32 { 1.5, 0.0, 0.0, 0.0 }
11 ADD TEMP[0], IN[0], IMM[0]
13 SUB OUT[0], TEMP[0], IMM[1]
Dfrag-tempx.sh8 IMM FLT32 { -0.5, -0.4, -0.6, 0.0 }
10 ADD TEMPX[0][0], IN[0], IMM[0]
11 ADD TEMPX[0][1], IN[0], IMM[0]
Dfrag-face.sh7 IMM FLT32 { 0.5, 1.0, 0.0, 0.0 }
9 MUL TEMP[0], IN[1].xxxx, IMM[0].xxxx
10 ADD TEMP[0], TEMP[0], IMM[0].yyyy
/external/pcre/dist/sljit/
DsljitNativeMIPS_32.c32 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar); in load_immediate()
35 return push_inst(compiler, ADDIU | SA(0) | TA(dst_ar) | IMM(imm), dst_ar); in load_immediate()
37 FAIL_IF(push_inst(compiler, LUI | TA(dst_ar) | IMM(imm >> 16), dst_ar)); in load_immediate()
38 …return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SL… in load_immediate()
44 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \
46 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
94 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); in emit_single_op()
112 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xffff), DR(dst)); in emit_single_op()
136 return push_inst(compiler, XORI | SA(EQUAL_FLAG) | TA(EQUAL_FLAG) | IMM(1), EQUAL_FLAG); in emit_single_op()
141 FAIL_IF(push_inst(compiler, BEQ | S(TMP_REG1) | TA(0) | IMM(5), UNMOVABLE_INS)); in emit_single_op()
[all …]
DsljitNativeMIPS_64.c38 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar); in load_immediate()
41 return push_inst(compiler, ADDIU | SA(0) | TA(dst_ar) | IMM(imm), dst_ar); in load_immediate()
44 FAIL_IF(push_inst(compiler, LUI | TA(dst_ar) | IMM(imm >> 16), dst_ar)); in load_immediate()
45 …return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SL… in load_immediate()
79 FAIL_IF(push_inst(compiler, LUI | TA(dst_ar) | IMM(uimm >> 48), dst_ar)); in load_immediate()
81 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 32), dst_ar)); in load_immediate()
89 …return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(i… in load_immediate()
114 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 48), dst_ar)); in load_immediate()
118 …return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(i… in load_immediate()
127 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \
[all …]
DsljitNativePPC_64.c52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
70 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
76 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
77 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp >> 32))); in load_immediate()
87 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
93 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
96 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp2)) : SLJIT_SUCCESS; in load_immediate()
[all …]
DsljitNativeSPARC_32.c30 return push_inst(compiler, OR | D(dst) | S1(0) | IMM(imm), DR(dst)); in load_immediate()
36 #define ARG2(flags, src2) ((flags & SRC2_IMM) ? IMM(src2) : S2(src2))
58 return push_inst(compiler, AND | D(dst) | S1(src2) | IMM(0xff), DR(dst)); in emit_single_op()
59 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst))); in emit_single_op()
60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); in emit_single_op()
70 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst))); in emit_single_op()
71 …return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)); in emit_single_op()
87 …FAIL_IF(push_inst(compiler, OR | (flags & SET_FLAGS) | D(dst) | S1(0) | IMM(32), UNMOVABLE_INS | (… in emit_single_op()
88 FAIL_IF(push_inst(compiler, OR | D(dst) | S1(0) | IMM(-1), DR(dst))); in emit_single_op()
92 FAIL_IF(push_inst(compiler, SLL | D(TMP_REG1) | S1(TMP_REG1) | IMM(1), DR(TMP_REG1))); in emit_single_op()
[all …]
DsljitNativePPC_32.c32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
193 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm))); in emit_single_op()
194 return push_inst(compiler, ORIS | S(dst) | A(dst) | IMM(compiler->imm >> 16)); in emit_single_op()
209 FAIL_IF(push_inst(compiler, XORI | S(src1) | A(dst) | IMM(compiler->imm))); in emit_single_op()
210 return push_inst(compiler, XORIS | S(dst) | A(dst) | IMM(compiler->imm >> 16)); in emit_single_op()
249 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(init_value >> 16))); in emit_const()
250 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(init_value)); in emit_const()
/external/compiler-rt/lib/builtins/arm/
Dudivsi3.S116 #define IMM # macro
119 cmp r0, r1, lsl IMM shift; \
121 WIDE(addhs) r3, r3, IMM (1 << shift); \
122 WIDE(subhs) r0, r0, r1, lsl IMM shift
Dudivmodsi4.S119 #define IMM # macro
122 cmp r0, r1, lsl IMM shift; \
124 WIDE(addhs) r3, r3, IMM (1 << shift); \
125 WIDE(subhs) r0, r0, r1, lsl IMM shift
/external/autotest/client/site_tests/network_SwitchCarrier/
Dnetwork_SwitchCarrier.py48 dbus_interface=self.IMM)
65 modems = self.mm.EnumerateDevices(dbus_interface=self.IMM)
76 self.IMM = 'org.freedesktop.ModemManager'
77 self.IMODEM_SIMPLE = self.IMM + '.Modem.Simple'

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