| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 104 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
113 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
128 multiclass ABSS_M<string opstr, InstrItinClass Itin,
130 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
132 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
[all …]
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| D | MicroMipsInstrInfo.td | 243 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
246 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
251 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
254 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
290 InstrItinClass Itin = NoItinerary> :
293 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
300 InstrItinClass Itin = NoItinerary,
304 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
309 InstrItinClass Itin = NoItinerary> :
311 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
[all …]
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| D | MipsCondMov.td | 20 InstrItinClass Itin> :
22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
28 InstrItinClass Itin> :
30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>,
36 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
41 Itin, FrmFR, opstr>, HARDFLOAT {
46 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
51 Itin, FrmFR, opstr>, HARDFLOAT {
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| D | MicroMips32r6InstrInfo.td | 516 InstrItinClass Itin = NoItinerary,
519 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
541 InstrItinClass Itin, bit isComm,
547 InstrItinClass Itinerary = Itin;
572 RegisterOperand SrcRC, InstrItinClass Itin,
579 InstrItinClass Itinerary = Itin;
603 InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
609 InstrItinClass Itinerary = Itin;
703 RegisterOperand SrcRC, InstrItinClass Itin,
710 InstrItinClass Itinerary = Itin;
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| D | MipsInstrInfo.td | 785 InstrItinClass Itin = NoItinerary,
789 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
797 InstrItinClass Itin = NoItinerary,
803 Itin, FrmI, opstr> {
853 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
855 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
863 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
865 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
871 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
872 StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 211 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); in initialize() local
216 Top.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG); in initialize()
217 Bot.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG); in initialize()
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| D | HexagonInstrInfoV4.td | 2629 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2634 "$Rd = $Rx", Itin> {
2654 InstrItinClass Itin> {
2655 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2656 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
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| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 2452 const InstrItineraryData *Itin = SchedModel->getInstrItineraries(); in initialize() local
2456 Itin, DAG); in initialize()
2461 Itin, DAG); in initialize()
3005 const InstrItineraryData *Itin = SchedModel->getInstrItineraries(); in initialize() local
3009 Itin, DAG); in initialize()
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