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Searched refs:MachineScheduler (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/CodeGen/
DMachineScheduler.cpp118 class MachineScheduler : public MachineSchedulerBase { class
120 MachineScheduler();
148 char MachineScheduler::ID = 0;
150 char &llvm::MachineSchedulerID = MachineScheduler::ID;
152 INITIALIZE_PASS_BEGIN(MachineScheduler, "machine-scheduler",
157 INITIALIZE_PASS_END(MachineScheduler, "machine-scheduler", in INITIALIZE_PASS_DEPENDENCY()
160 MachineScheduler::MachineScheduler() in INITIALIZE_PASS_DEPENDENCY()
165 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { in getAnalysisUsage()
272 ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() { in createMachineScheduler()
316 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { in runOnMachineFunction()
DAndroid.mk77 MachineScheduler.cpp \
DCMakeLists.txt81 MachineScheduler.cpp
/external/llvm/test/CodeGen/X86/
Dmisched-new.ll9 ; Interesting MachineScheduler cases.
D2012-11-30-misched-dbg.ll4 ; Test MachineScheduler handling of DBG_VALUE.
Dmisched-matmul.ll4 ; Verify that register pressure heuristics are working in MachineScheduler.
/external/llvm/lib/Target/AArch64/
DAArch64SchedA53.td16 // This works with MachineScheduler. See MCSchedModel.h for details.
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td16 // required until SD and PostRA schedulers are replaced by MachineScheduler.
DARMScheduleA9.td16 // required until SD and PostRA schedulers are replaced by MachineScheduler.
1880 // This works with MachineScheduler and will eventually replace itineraries.