| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 534 ISD::MemIndexedMode &AM, bool &IsInc,
537 ISD::MemIndexedMode &AM,
540 SDValue &Offset, ISD::MemIndexedMode &AM,
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| D | AArch64ISelLowering.cpp | 9740 ISD::MemIndexedMode &AM, in getIndexedAddressParts()
9762 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
9784 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const { in getPostIndexedAddressParts()
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| D | AArch64ISelDAGToDAG.cpp | 1045 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectIndexedLoad()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 172 ISD::MemIndexedMode &AM,
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| D | MSP430ISelDAGToDAG.cpp | 301 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
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| D | MSP430ISelLowering.cpp | 1108 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 798 enum MemIndexedMode { enum
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| D | SelectionDAGNodes.h | 710 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1924 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
1940 ISD::MemIndexedMode getAddressingMode() const {
1941 return ISD::MemIndexedMode((SubclassData >> 2) & 7);
1960 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1988 SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
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| D | SelectionDAG.h | 847 SDValue Offset, ISD::MemIndexedMode AM);
848 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
855 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
875 SDValue Offset, ISD::MemIndexedMode AM);
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 309 ISD::MemIndexedMode &AM,
316 SDValue &Offset, ISD::MemIndexedMode &AM,
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| D | ARMISelDAGToDAG.cpp | 907 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg()
943 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre()
963 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm()
1042 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset()
1137 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1362 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset()
1472 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectARMIndexedLoad()
1545 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectT2IndexedLoad()
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| D | ARMISelLowering.cpp | 11078 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
11117 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 192 ISD::MemIndexedMode &AM,
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| D | HexagonISelDAGToDAG.cpp | 492 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad()
597 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
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| D | HexagonISelLowering.cpp | 909 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 863 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
873 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
899 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
905 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
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| D | TargetLowering.h | 2051 ISD::MemIndexedMode &/*AM*/, in getPreIndexedAddressParts() argument
2062 ISD::MemIndexedMode &/*AM*/, in getPostIndexedAddressParts() argument
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 459 ISD::MemIndexedMode &AM,
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| D | PPCISelLowering.cpp | 1869 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 361 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName()
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| D | SelectionDAG.cpp | 556 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile, in encodeMemSDNodeFlags()
5039 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
5072 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
5164 SDValue Offset, ISD::MemIndexedMode AM) { in getIndexedLoad()
5299 SDValue Offset, ISD::MemIndexedMode AM) { in getIndexedStore()
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| D | DAGCombiner.cpp | 9579 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore()
9806 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore()
9886 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SplitIndexingFromLoad()
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